Design of 6.25 Gb/s SerDes Receiver

TIAN Xiao; HE Yan-dong

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Design of 6.25 Gb/s SerDes Receiver

更新时间：2026-09-04

- Design of 6.25 Gb/s SerDes Receiver
- Vol. 34, Issue 7, Pages: 119-122(2017)
- 作者机构：
  
  北京大学微电子研究院,北京,100871
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
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田啸, 何燕冬. 6.25 Gb/s串行数据接收器设计[J]. 微电子学与计算机, 2017, 34(7): 119-122.

TIAN Xiao, HE Yan-dong. Design of 6.25 Gb/s SerDes Receiver[J]. 2017, 34(7): 119-122.
田啸, 何燕冬. 6.25 Gb/s串行数据接收器设计[J]. 微电子学与计算机, 2017, 34(7): 119-122. DOI：

TIAN Xiao, HE Yan-dong. Design of 6.25 Gb/s SerDes Receiver[J]. 2017, 34(7): 119-122. DOI：

摘要

设计一款基于65 nm CMOS工艺、数据传输速率在6.25 Gb/s的SerDes接收器

其中均衡电路采用连续时间线性均衡器; 采样电路采用了一种新型灵敏放大器

较传统结构将灵敏度提升了一个量级

同时解决了传统结构输出信号下降沿比上升沿慢一个门延迟的问题; 时钟数据恢复电路(CDR)采用半速率采样二阶CDR系统实现.通过仿真验证

该接收器具有正确逻辑功能

功耗为10.2 mW.

Abstract

In this paper

a 65 nm CMOS 6.25 Gb/s SerDes receiver is designed. Equalization is achieved by using continuous-time linear equalizer. The sampler employs a novel sense amplifier(SA)

which improves the sensitivity by the conventional SA of magnitude and simultaneously solves the problem that falling edge lags rising edge the time of a gate delay; a half-rate second order clock and data recovery system is presented. Simulation results show that the receiver has the correct logic function

the power consumption is 10.2 mW.

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Keywords

references

Nikolic B, Oklobdzijia V, Stojanovic V, et al. Improved sense-amplifier based flip-flop: design and measurements[J]. IEEE J. Solid-State Circuits, 2000, 35(6): 876-883. DOI: 876

Sonntag Jeff L, John Stonick. A digital clock and data recovery architecture for multi-gigabit/s binary links[J]. IEEE J. Solid-State Circuits, 2006, 41 (8): 1867-1875. DOI: 1867

He Mike Yun, John Poulton. A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver[J]. IEEE J. Solid-State Circuits, 2006, 41(3): 597-606. DOI: 597

Gondi Srikanth, Behzad Razavi. Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers[J]. IEEE J. Solid-State Circuits, 2007, 42 (9) : 1999-2011. DOI: 1999

Matsui M, Hara H, Uetani Y, et al. A 200 MHz 13 mm 2-D DCT macrocell using sense amplifying pipeline flip-flop scheme[J]. IEEE J. Solid-State Circuits, 1994, 29: 1482-1490. DOI: 1482

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