Design of NoC Router Based on High Speed Data Acquisition

XU Chuan-pei; LIU Biao

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Design of NoC Router Based on High Speed Data Acquisition

更新时间：2026-09-04

- Design of NoC Router Based on High Speed Data Acquisition
- Vol. 34, Issue 11, Pages: 140-144(2017)
- 作者机构：
  
  桂林电子科技大学机构电子工程与自动化学院, 广西自动检测技术与仪器重点实验室,广西,桂林,541004
- 作者简介：
- 基金信息：
- DOI：
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- Published：2017
- 稿件说明：
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许川佩, 刘标. 基于高速数据采集的NoC路由器设计[J]. 微电子学与计算机, 2017, 34(11): 140-144.

XU Chuan-pei, LIU Biao. Design of NoC Router Based on High Speed Data Acquisition[J]. 2017, 34(11): 140-144.
许川佩, 刘标. 基于高速数据采集的NoC路由器设计[J]. 微电子学与计算机, 2017, 34(11): 140-144. DOI：

XU Chuan-pei, LIU Biao. Design of NoC Router Based on High Speed Data Acquisition[J]. 2017, 34(11): 140-144. DOI：

摘要

针对NoC数据处理量越来越大

确定性算法在数据量较大时

数据包传输延迟增大

而简单的自适应算法占用过多的片上资源等问题

将改进XY自适应算法应用在片上网络中

节点设计基于2D_Mesh拓扑结构、虚通道技术的虫洞交换模式.采用VerilogHdl语言完成NoC路由节点中各个模块的设计

并在Modelsim软件上进行仿真

最终在FPGA上实现NoC路由器功能.实验结果表明

设计的路由器能够满足高速数据的处理

且不会有延迟、死锁等问题的发生.

Abstract

Since the quantity of data process for NoC is more and more large

the packet transmission delay is increased with the deterministic algorithm. However

the simple adaptive algorithm takes too many on-chip resources.To solve the problems

the improved XY adaptive routing algorithm is adopted in this paper. We design node based on 2D_Mesh topology structure and wormhole switching mode of virtual channel technology. In addition

VerilogHdl language is used to complete the design of each part function for NoC routing node. Finally

the simulation experiment is carried out on Modelsim software and the function of NoC routing node is implemented on FPGA. Experimental results show that

the router designed in this paper can satisfy the process of high speed data and avoid the delay and deadlock issues.

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Keywords

references

贾佳. 基于NoC的改进XY自适应路由算法的设计[D]. 西安: 西安电子科技大学, 2011.

Zhu J Y, Qian Z L, Tsui C Y. A high performance NoC router architecture using bi-directional link with double data [J]. Integration-the Vlsi Journal, 2016: 30-42. DOI: 30

Wu W T, Louri A. A Methodology for cognitive NoC design[C]//IEEE Computer Architecture Letters. IEEE, 2015: 1-4.

王荣阳, 袁泉, 陈栋, 王科. 基于FPGA的32位片上网络设计与验证[J]. 航空电子技术, 2015, 46(3): 42-46. DOI: 42

许川佩, 邱凭婷, 万春霆. 基于FPGA的片上网络路由器并行测试研究[J]. 微电子学与计算机, 2015, 32(12): 163-168. DOI: 163

许川佩, 仁智新. 基于FPGA的NoC路由器的设计[J]. 微电子学与计算机, 2012, 29(8): 53-57. DOI: 53

张颖, 吴宁, 葛芬. 基于路径的无死锁NoC多播路由器的设计[J]. 微电子学与计算机, 2014, 30(11): 1-5. DOI: 1

岳峰, 李润丰, 陈田, 刘军等. 基于随机路由的高性能片上路由器设计与仿真[J]. 电子测量与仪器学报, 2013, 27(7): 22-26. DOI: 22

欧阳一鸣, 董少周, 梁华国. 基于2D Mesh的NoC路由算法设计与仿真[J]. 计算机工程, 2009, 35(11): 227-235. DOI: 227

万玉鹏, 吴宁. 基于自适应算法的NoC路由单元的系统级设计[J]. 微电子学与计算机, 2010, 27(5): 42-49. DOI: 42

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