Design of a Novel Radiation-hardened SR Latch

SU Lin; WANG Jia; GAO Wu; ZHENG Ran; WEI Xiao-min; HU Yong-cai

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Design of a Novel Radiation-hardened SR Latch

更新时间：2026-09-04

- Design of a Novel Radiation-hardened SR Latch
- Vol. 34, Issue 9, Pages: 136-140(2017)
- 作者机构：
  
  1. 西北工业大学计算机学院,陕西,西安,710072
  2. 斯特拉斯堡大学, 法国斯特拉斯堡,67037
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2017
- 稿件说明：
移动端阅览
苏霖, 王佳, 高武, 郑然, 魏晓敏, 胡永才. 一种新颖的抗辐射加固SR锁存器设计[J]. 微电子学与计算机, 2017, 34(9): 136-140.

SU Lin, WANG Jia, GAO Wu, et al. Design of a Novel Radiation-hardened SR Latch[J]. 2017, 34(9): 136-140.
苏霖, 王佳, 高武, 郑然, 魏晓敏, 胡永才. 一种新颖的抗辐射加固SR锁存器设计[J]. 微电子学与计算机, 2017, 34(9): 136-140. DOI：

SU Lin, WANG Jia, GAO Wu, et al. Design of a Novel Radiation-hardened SR Latch[J]. 2017, 34(9): 136-140. DOI：

摘要

为了设计出抗辐射加固的DC-DC开关电源振荡器

其中SR锁存器的抗辐射性能至关重要

提出了一种新颖的抗辐射加固SR锁存器电路.该抗辐射加固SR锁存器基于空间冗余设计的思想

已经在标准商用2P5M 0.25 μm工艺下设计和验证

电路版图面积为130 μm×50 μm

能够抗最大的总剂量效应为100 kRad(Si)

可以承受的最大线性能量传输LET为85 MeV-cm/mg.相比于三模冗余SR锁存器

所设计的抗辐射加固SR锁存器电路的晶体管数目更少

电路节点的临界电荷更大

在电路节点同时发生多处翻转的情况下

抗单粒子翻转的成功率更高.

Abstract

In order to design the radiation-hardened oscillator of the DC-DC converter

in which the radiation-hardened performance of the SR latch is very important

a novel radiation-hardened SR latch is presented in this paper. The proposed radiation-hardened SR latch is based on space redundancy and has been designed and verified in a standard commercial 2P5M 0.25 m process. The die area of the latch is 130 m×50 m. Total ionizing dose tolerance is 100kRad(Si) and single event effect immuning to LET is 85MeV-cm/mg. Compared with the triple modular redundancy SR latch

the proposed radiation-hardened SR latch has less transistors

larger critical charge of the circuit node and higher success rate of the circuit immuning to single event upset when more than one circuit nodes are upset at the same time.

关键词

Keywords

references

Tong Lin. Experimental Investigation into Radiation- Hardening-By-Design (RHBD) Flip-Flop Designs in a 65nm CMOS Process[C]// 2016 IEEE International Symposium on Circuits and Systems: . IEEE, 2016: 966-969.

韩郑生. 抗辐射集成电路概论[M]. 北京: 清华大学出版社, 2008: 1-20, 83, 181. DOI: 1

Guilherme S. Cardoso, Tiago R. Balen. Study of layout accuracy on W/L estimation of ELT in analog design flow[C]// 2016 IEEE 7th Latin American Symposium on Circuits % Systems. IEEE, 2016: 279-282.

胡明浩. 基于RHBD技术CMOS锁存器加固电路的研究[J]. 微电子学与计算机, 2010, 28(27): 206-209. DOI: 206

Chen Tai-Hua. Ultra-low power radiation hardened by design memory circuits[J]. IEEE Transactions on Nuclear Science, 2007(54): 2004-2011. DOI: 2004

Liu M N, Whitaker S. Low power SEU immune CMOS memory circuits[J]. IEEE Transactions on Nuclear Science, 1992(39): 1679-1684. DOI: 1679

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