A Digital-Controlled Silicon Neuron Circuit

CHENG Ze-jun; LI Bin-hong; LI Bo; LUO Jia-jun; HAN Zheng-sheng

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A Digital-Controlled Silicon Neuron Circuit

更新时间：2026-09-04

- A Digital-Controlled Silicon Neuron Circuit
- Vol. 36, Issue 1, Pages: 6-10(2019)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,101408
  3. 中国科学院硅器件与技术重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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程泽军, 李彬鸿, 李博, 罗家俊, 韩郑生. 一种基于数字信号控制的CMOS神经元电路[J]. 微电子学与计算机, 2019, 36(1): 6-10, 15.

CHENG Ze-jun, LI Bin-hong, LI Bo, et al. A Digital-Controlled Silicon Neuron Circuit[J]. 2019, 36(1): 6-10.
程泽军, 李彬鸿, 李博, 罗家俊, 韩郑生. 一种基于数字信号控制的CMOS神经元电路[J]. 微电子学与计算机, 2019, 36(1): 6-10, 15. DOI：

CHENG Ze-jun, LI Bin-hong, LI Bo, et al. A Digital-Controlled Silicon Neuron Circuit[J]. 2019, 36(1): 6-10. DOI：

摘要

采用0.18 μm CMOS工艺设计了一种由数字信号控制的神经元电路.相比于传统神经元电路

本电路不需要偏置电压

控制简单

便于大规模集成.在数字信号的控制下

本电路可以方便地实现Regular Spiking (RS)

Fast Spiking (FS)

Chattering (CH)

Intrinsic Bursting (IB)四种神经元脉冲响应模式.此外本文介绍了一种激励型突触电路

该电路的突触权值可以通过基于脉冲的Spike Driven Synaptic Plasticity(SDSP)学习机制进行调节.在此基础上本文利用3个神经元与2个突触实现了Pavlov实验

证明了所设计的神经元电路支持SDSP学习规则

可以用于构建神经形态硬件.

Abstract

A digital controlled neuron circuit which mimics properties of biological neuron is presented using 0.18 μm CMOS technology. Compared with other neuron circuits

the proposed one does not require a bias voltage

which facilitates circuit control and is beneficial to large-scale integration. Under the control of digital signals

the proposed circuit can easily generate four types of firing patterns: Regular Spiking (RS)

Fast Spiking (FS)

Chattering (CH)

and Intrinsic Bursting (IB). In addition

we design an excitatory synapse circuit whose synaptic weight can be adjusted according to Spike Driven Synaptic Plasticity (SDSP) learning algorithm. Furthermore

we implement Pavlov experiment with three neurons and two synapses. The experimental result demonstrates that this neuron circuit supports SDSP learning algorithm and can be used in neuromorphic hardware.

关键词

Keywords

references

Giacomo Indiveri, Shih Chii Liu. Memory and information processingin neuromorphic systems [J]. Proceedings of the IEEE, 2015, 103(8): 1379-1397. DOI: 1379

Eugene M Izhikevich. Simple model of spiking neurons [J]. IEEE Transactions on Neural Networks, 2003, 14(6): 1569-1572. DOI: 1569

Mead C. Neuromorphic electronic systems [J]. Proceedings of the IEEE, 1990, 78(10): 1629-1636. DOI: 1629

Abbott L. Lapicque's introduction of the integrate-and-fire model neuron [J]. Brain Research Bulletin, 1999, 50(5): 303-304. DOI: 303

Qiao N. A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses [J]. Front. Neurosci, 2015, 141 (9): 1-17. DOI: 1

Young Jun Lee. Low power real time electronic neuron VLSI design using subthreshold technique [C]//IEEE International Symposium on Circuits and Systems. San Diego, La Jolla, CA, USA, 2004: 744-747.

李传东.脉冲神经网络的忆阻器突触联想学习电路分析[J].重庆大学学报, 2014, 37(7): 115-124. DOI: 115

Joubert A. Hardware spiking neurons design: analog or digital [C]//International Joint Conference on Neural Networks (IJCNN). Brisbane, QLD, Australia, 2012: 11-15.

Hodgkin A, Huxley A. A quantitative description of membranecurrent and its application to conduction and excitation in nerve[J]. TheJournal of Phisiology, 1952, 117(4): 500-544. DOI: 500

Jayawan H B Wijekoon. Compact silicon neuron circuit with spiking and bursting behavior [J]. Neural Networks, 2008, 21(1): 524-534. DOI: 524

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