Vertex Shader Processor Design Based on Very Long Instruction Word

XU Qi-chao; DU Hui-min; LIU Qing-nan

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Vertex Shader Processor Design Based on Very Long Instruction Word

更新时间：2026-09-04

- Vertex Shader Processor Design Based on Very Long Instruction Word
- Vol. 35, Issue 10, Pages: 13-18(2018)
- 作者机构：
  
  西安邮电大学机构电子工程学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
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- Published：2018
- 稿件说明：
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徐起超, 杜慧敏, 刘青楠. 基于超长指令字的顶点染色处理器设计[J]. 微电子学与计算机, 2018, 35(10): 13-18.

XU Qi-chao, DU Hui-min, LIU Qing-nan. Vertex Shader Processor Design Based on Very Long Instruction Word[J]. 2018, 35(10): 13-18.
徐起超, 杜慧敏, 刘青楠. 基于超长指令字的顶点染色处理器设计[J]. 微电子学与计算机, 2018, 35(10): 13-18. DOI：

XU Qi-chao, DU Hui-min, LIU Qing-nan. Vertex Shader Processor Design Based on Very Long Instruction Word[J]. 2018, 35(10): 13-18. DOI：

摘要

为了提高嵌入式图形处理器GPU(Graphic Process Unit)中顶点染色处理器

设计了一款超长指令字格式的可编程顶点染色处理器

采用六级流水线实现

每条指令在同一个周期最多执行7种操作

软硬件协同设计

降低了功耗.采用基于FPGA的验证方式

可编程顶点染色处理器在Xilinx Virtex-7 FPGAs V2000T上最大工作频率达到50 MHz

顶点的处理速度达到0.16 M/s

处理一个顶点平均44个周期

在Synopsys公司Design Compiler工具130 μm工艺综合下

主频150 MHz

功耗约为177.742 8 mW.

Abstract

In order to improve the vertex shader processor in the Graphic Process Unit (GPU)

a programmable vertex shader processor with a very long instruction word format is designed and implemented in a six-stage pipeline. Each instruction has a maximum of one cycle Implementation of seven kinds of operations

hardware and software co-design

reducing power consumption. Using FPGA-based verification

the programmable vertex shader processor achieves a maximum operating frequency of 50 MHz on the Xilinx Virtex-7 FPGAs V2000T

a vertex processing speed of 0.16 M/s

and an average of 44 cycles for a vertex. At Synopsys Design Compiler tools 130 μm process synthesis

clocked at 150 MHz

power consumption is about 177.7428 mW.

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references

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