Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol

YANG Chao-xiang; KONG Xian-wei; LUAN Wen-huan; ZHANG Yuan-hang; WANG Zhi-jun; ZHANG Chun; WANG Zi-qiang

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Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol

更新时间：2026-09-04

- Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol
- Vol. 36, Issue 2, Pages: 16-20(2019)
- 作者机构：
  
  1. 清华大学微电子学研究所,北京,100084
  2. 中国电子技术标准化研究院集成电路测试与评价工业和信息化部重点实验室,北京,100176
- 作者简介：
- 基金信息：
- DOI：
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- Published：2019
- 稿件说明：
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杨钞翔, 孔宪伟, 栾文焕, 张远航, 王志军, 张春, 王自强. 基于以太网10Gbase-R协议的PCS层设计[J]. 微电子学与计算机, 2019, 36(2): 16-20.

YANG Chao-xiang, KONG Xian-wei, LUAN Wen-huan, et al. Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol[J]. 2019, 36(2): 16-20.
杨钞翔, 孔宪伟, 栾文焕, 张远航, 王志军, 张春, 王自强. 基于以太网10Gbase-R协议的PCS层设计[J]. 微电子学与计算机, 2019, 36(2): 16-20. DOI：

YANG Chao-xiang, KONG Xian-wei, LUAN Wen-huan, et al. Design of the Physical Coding Sublayer Based on the Ethernet 10Gbase-R Protocol[J]. 2019, 36(2): 16-20. DOI：

摘要

随着网络技术的飞速发展

以太网技术凭借其优良特性已经成为当今使用最广泛的局域网技术

以太网标准包含多种协议构成完整体系

10Gbase-R协议作为其中重要的基础协议得到重视.本文基于10Gbase-R协议的PCS层

深入探究PCS层内部关键模块:弹性缓冲器、64B/66B编解码器、加解扰码器、位宽转换器等

提出完整设计架构

使用verilog语言完成其RTL级模块设计

搭建仿真验证平台

使用Modelsim软件进行功能验证

完成了相关设计.

Abstract

With the rapid development of network technology

Ethernet technology has become the most widely used local area network technology with its excellent features. The Ethernet standard consists of multiple protocols to form a complete system. The 10Gbase-R protocol is one of the important basic protocol. This article is based on the PCS layer of the 10Gbase-R protocol

and deeply explores the key modules within the PCS layer: elastic buffers

64B/66B codecs

scrambler/descrambler

bit-width converters

etc. It proposes a complete design architecture

and uses the verilog language to complete the RTL-level module design

then builds simulation verification platform and uses modelsim software to complete the functional verification

and completes related design.

关键词

Keywords

references

Michelogiannakis G, Balfour J, Dally W J. Elastic-buffer flow control for on-chip networks[C]// IEEE, International Symposium on High PERFORMANCE Computer Architecture. IEEE, 2009: 151-162.

Law D, Dove D, D'Ambrosia J, et al. Evolution of ethernet standards in the IEEE 802.3 working group[J]. Communications Magazine IEEE, 2013, 51(8):88-96. DOI: 88

Verilog E, Cummings C E, Simulation and Synthesis Techniques for Asynchronous FIFO Design[J]. Snug, 2002, 2(3):1-18. DOI: 1

D'Ambrosia J. Defining the next generation of ethernet[J]. Communications Magazine IEEE, 2008, 45(11):38-38. DOI: 38

Lin C H, Chen C N, Wang Y J, et al. Parallel scrambler for high-speed applications[J]. IEEE Transactions on Circuits %Systems II Express Briefs, 2006, 53(7):558-562. DOI: 558

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Related Author

DING Li

Related Institution

School of Information and Control Engineering,Xi′an Architecture and Technology University,Xi′an 7100551

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