A Implementation Method of Multi-core Task Monitoring Mechanism Based on Cache Consistency

CHEN Hui; MU Fu-qi; ZHANG Ran; JIANG Bin

Chinese

您当前的位置：

首页 >

文章列表页 >

A Implementation Method of Multi-core Task Monitoring Mechanism Based on Cache Consistency

更新时间：2026-09-04

- A Implementation Method of Multi-core Task Monitoring Mechanism Based on Cache Consistency
- Vol. 35, Issue 10, Pages: 19-22(2018)
- 作者机构：
  
  1. 中国科学院大学机构微电子学院,北京,100049
  2. 江苏中科羿链通信技术有限公司,江苏,无锡,214135
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
移动端阅览
陈慧, 慕福奇, 张然, 姜彬. 一种基于cache一致性的多核任务监测机制的实现方法[J]. 微电子学与计算机, 2018, 35(10): 19-22, 28.

CHEN Hui, MU Fu-qi, ZHANG Ran, et al. A Implementation Method of Multi-core Task Monitoring Mechanism Based on Cache Consistency[J]. 2018, 35(10): 19-22.
陈慧, 慕福奇, 张然, 姜彬. 一种基于cache一致性的多核任务监测机制的实现方法[J]. 微电子学与计算机, 2018, 35(10): 19-22, 28. DOI：

CHEN Hui, MU Fu-qi, ZHANG Ran, et al. A Implementation Method of Multi-core Task Monitoring Mechanism Based on Cache Consistency[J]. 2018, 35(10): 19-22. DOI：

摘要

为了解决在多核多操作系统这种情况下任务监测的不便

尤其是要处理某核运行异常

仍要有效的捕获和分析该核上的任务状况等问题

提出了一种基于cache一致性的多核任务监测机制的实现方法

对任务使用系统资源及自身运行状态与堆栈信息的监测.最后以Zynq-7000为硬件平台

在Linux和FreeRTOS双系统的模式下

进行试验测试

结果表明该机制能有效的监测多核系统的任务状况

为任务管理和异常处理提供方便.

Abstract

In order to solve the problem of task monitoring

it is necessary to effectively capture and analyze the problems of the tasks in the core

such as the operation of a exceptional core. In the paper

a multi-core task monitoring mechanism based on cache consistency is proposed to realize the monitoring of the system resources and the operation status and stack information of the task. Then conducting the experimental test on the ZYNQ-7000 platform. In the double system mode of Linux and FreeRTOS

the results show that the mechanism can effectively monitor the multi-core system task status

provide convenience for task management and exception handling.

关键词

Keywords

references

Amer Diwan, David Tarditi, Eliot Moss. Memory system performance of programs with intensive heap allocation[J]. ACM Transactions on Computer Systems (TOCS), 1995, 13(3):244-273. DOI: 244

蔡玉鑫.嵌入式多核处理器核间通信方法的设计与实现[D].西安: 西安电子科技大学, 2015.

郭海林, 陈香兰.一种支持多级存储架构的嵌入式多核操作系统模型[J].计算机系统应用, 2015, 24(12):110-117. DOI: 110

Dalui M, Som T, Bansal S, et al. Handling cache write-back and cache eviction for cache coherence[P]. WO2014022397, 2014-02-06. United States Patent Application 20140040561.

孙荪.提高多核处理器片上Cache利用率的关键技术研究[D].合肥: 中国科学技术大学, 2015.

刘文佳.多核处理器Cache一致性研究与设计[D].哈尔滨: 哈尔滨工程大学, 2010.

黄安文, 张民选.多核处理器Cache一致性协议关键技术研究[J].计算机工程与科学, 2009, 31(S1):104-108. DOI: 104

王欣, 邱昕, 慕福奇, 等.基于MCAPI的嵌入式多核通信机制的研究[J].微电子学与计算机, 2017, 34(11):85-88. DOI: 85

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design and implementation of high performance SIMT processor storage system for machine learning

Real-time optimization and reliability Realization of embedded Linux based on Loonson 1E

Design and Implementation of Control Element of RV32I

The Design and Implementation of the Network Management System of the Dual Stack Based on Linux Platform

The Cache Management Strategy Research on RAID Controller System

Related Author

XU Xiao-yan

XING Li-dong

LI Tao

SUN Zhe

ZHOU Qing

WANG Pu

LI Tao

LIANG Qing

Related Institution

School of Electornic Engineering, Xi'an University of Posts and Telecommunications

School of Computer Science and Technology, University of Chinese Academy of Sciences

National Space Science Center, CAS

School of Electronic Engineering, Xi'an University of Posts and Telecommunications

College of Computer, Northwestern Polytechnical University

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰