A Universal Embeded Digital IP Core Testing Method

MA Xin-yu; XU Han-yang; WANG Jian

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A Universal Embeded Digital IP Core Testing Method

更新时间：2026-09-04

- A Universal Embeded Digital IP Core Testing Method
- Vol. 36, Issue 2, Pages: 26-30(2019)
- 作者机构：
  
  复旦大学专用集成电路和系统国家重点实验室,上海,201203
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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马昕煜, 徐瀚洋, 王健. SOC嵌入式数字IP核通用测试方法[J]. 微电子学与计算机, 2019, 36(2): 26-30.

MA Xin-yu, XU Han-yang, WANG Jian. A Universal Embeded Digital IP Core Testing Method[J]. 2019, 36(2): 26-30.
马昕煜, 徐瀚洋, 王健. SOC嵌入式数字IP核通用测试方法[J]. 微电子学与计算机, 2019, 36(2): 26-30. DOI：

MA Xin-yu, XU Han-yang, WANG Jian. A Universal Embeded Digital IP Core Testing Method[J]. 2019, 36(2): 26-30. DOI：

摘要

本文基于IEEE标准设计了一种通用的、低成本的嵌入式IP核测试方法.该方法通过仅重新定义待测IP的端口数量和名称

即可完成各种数字IP核测试电路设计以及集成

该方法支持IEEE1500标准中的所定义的全部11条通用指令所对应的工作模式

以此来提供丰富的IP核测试控制以及观测模式; 测试软件兼容符合IEEE1687的测试数据

可做到无需修改测试图形文件即可自动完成测试、提取诊断信息.为了验证本方法的有效性

我们在FPGA上实现并测试了多种异构IP核和大量的同构IP核

在整个测试过程中

该测试方法在保证支持国际主流测试标准、具有较高的测试自动化程度的同时

利用其通用性简化了数字IP核的测试集成和复用过程.

Abstract

This paper presents a general

low cost embedded IP core testing method based on IEEE standards. Only by redefining the number and name of under-test IP cores

the method can automatically generate test wrappers for various digital IP cores. The test wrapper supports all 11 instructions specified in the IEEE 1500 standard

thereby providing ample IP core test control and observation modes. The test software is IEEE1687-compatible

when the IP core is tested in different SOC designs

it can automatically complete the test and extract diagnostic information without modifying the test pattern. In order to verify this method

we implemented and tested a variety of heterogeneous IP cores and a large number of homogeneous IP cores on FPGA. This test method simplifies the test integration and reuse process of the digital IP cores by supporting mainstream IEEE test standards and providing a high degree of test automation.

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references

Lee K J, Hsieh T Y, Chang C Y, et al. On-Chip SOC Test Platform Design Based on IEEE 1500 Standard[J]. IEEE Transactions on Very Large Scale Integration Systems, 2010, 18(7):1134-1139. DOI: 1134

Kajihara S, Sasao T. On the adders with minimum tests[C]// Asian Test Symposium. IEEE Computer Society, 1997: 10.

黃瑜真.用於多核心/裸晶系統晶片之有效測試與良率提升技術[D].首尔: 中央大學, 2012.

Ali G, Hussin F A, Ali N B Z, et al. Enhancement in IEEE 1500 standard for at-speed test and debug[C]// Circuits and Systems Conference. IEEE, 2014: 1-4.

Huang Y J, Li J F. Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers[J]. IEEE Transactions on Very Large Scale Integration Systems, 2012, 20(11):2123-2127. DOI: 2123

Zhang Z, Lai J. An efficient method for testing multipliers of embedded DSPs in FPGA[C]// IEEE International Conference on Solid-State and Integrated Circuit Technology. IEEE, 2017: 695-697.

IEEE Standard Testability Method for Embedded Core-based Integrated Circuits[C]// IEEE Std. IEEE, 2005: 2.

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device[C]// IEEE Std. IEEE, 2014: 2.

Hamdioui S, Goor A J V D, Rodgers M. March SS: A Test for All Static Simple RAM Faults[C]// IEEE International Workshop on Memory Technology, Design and Testing. IEEE, 2002: 95-100.

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