XING Zong-qi, HE Zhan-zhuang, XU Dan-ni, et al. Design and Implementation of a Parallel PCS Sublayer Frame Synchronization Detection Module[J]. 2018, 35(11): 38-42.
XING Zong-qi, HE Zhan-zhuang, XU Dan-ni, et al. Design and Implementation of a Parallel PCS Sublayer Frame Synchronization Detection Module[J]. 2018, 35(11): 38-42.DOI:
Design and Implementation of a Parallel PCS Sublayer Frame Synchronization Detection Module
In order to meet the needs of PCS sublayer frame synchronization at 10 Gbps transmission rate
depth studying of 10 G Ethernet PCS sublayer frame synchronization principle and common frame synchronization detection method
considering the chip area and detection efficiency
a parallel frame synchronization detection module is designed
which solves the problems of the synchronous header cross data blocks and the alignment of bits in the frame synchronization detection
improves the frame synchronization efficiency
and can meet the requirements of the 10 Gbps frame synchronization of the PCS sublayer. ModelSim is used to verify the design of the frame synchronization detection module
the results show that the module can effectively achieve the 10 Gbps PCS sublayer frame synchronization detection function
the frame synchronization speed is markedly improved
with strong adaptability
robustness and stability.
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references
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