Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL

WANG Zheng-chen; WANG Xing-hua; WU Zhao-bo

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Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL

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- Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL
- Vol. 35, Issue 6, Pages: 47-51(2018)
- 作者机构：
  
  北京理工大学信息与电子学院北京市硅基高速片上系统工程技术研究中心,北京,100081
- 作者简介：
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- Published：2018
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王征晨, 王兴华, 武照博. 一种低相噪低杂散1.08GHz锁相环设计[J]. 微电子学与计算机, 2018, 35(6): 47-51.

WANG Zheng-chen, WANG Xing-hua, WU Zhao-bo. Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL[J]. 2018, 35(6): 47-51.
王征晨, 王兴华, 武照博. 一种低相噪低杂散1.08GHz锁相环设计[J]. 微电子学与计算机, 2018, 35(6): 47-51. DOI：

WANG Zheng-chen, WANG Xing-hua, WU Zhao-bo. Design of a Low Phase Noiseand Low Spur 1.08 GHz PLL[J]. 2018, 35(6): 47-51. DOI：

摘要

基于TSMC90 nm CMOS工艺设计了一款高性能锁相环.深入分析了电荷泵的噪声和杂散性能

讨论了LC压控振荡器的锁定范围理论计算以及相位噪声

并且给出了环路滤波器的设计方法.通过MATLAB软件对锁相环整体相位噪声进行系统建模与分析

以优化锁相环的整体相位噪声.整体芯片面积为530 μm×720 μm

功耗为33 mW.测试结果表明

在频偏1 MHz处的相位噪声为-110.6 dBc

参考杂散-56.935 dBc.

Abstract

A high performance PLL (Phase Locked Loop) is designed and implemented in TSMC 90 nm CMOS Process. The noise and reference spur of the charge pump are analyzed in detail. The theoretical calculation of LC VCO (Voltage Controlled Oscillator) turning range is presented and its phase noise is discussed. The design methods of loop filter is studied. In order to optimize phase noise

the PLL is analyzed by MATLAB. The PLL proposed consumes 33 mW with a 1.2 V power supply and only occupies an area of 530 μm×720 μm. The measured results show that it exhibits an in-band phase noise of -110.6 dBc at 1MHz frequency offset and reference spur is -56.935 dBc.

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references

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杨振宇.频率综合器相位噪声分析及全差分电荷泵设计[D].上海: 复旦大学, 2007.

陈海波, 孟桥, 李冬.应用于无线通信收发系统锁相环的研究[J].电子器件, 2016, 39(4): 874-877. DOI: 874

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