Full-Speed Test Design Based on Memory Built-in Self-test

ZHANG Li-bo; TANG Wei; YAN Wei; Li Jun-ling

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Full-Speed Test Design Based on Memory Built-in Self-test

更新时间：2026-09-04

- Full-Speed Test Design Based on Memory Built-in Self-test
- Vol. 35, Issue 11, Pages: 43-46(2018)
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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张立博, 唐威, 颜伟, 李俊玲. 基于存储器内建自测试的全速测试设计[J]. 微电子学与计算机, 2018, 35(11): 43-46.

ZHANG Li-bo, TANG Wei, YAN Wei, et al. Full-Speed Test Design Based on Memory Built-in Self-test[J]. 2018, 35(11): 43-46.
张立博, 唐威, 颜伟, 李俊玲. 基于存储器内建自测试的全速测试设计[J]. 微电子学与计算机, 2018, 35(11): 43-46. DOI：

ZHANG Li-bo, TANG Wei, YAN Wei, et al. Full-Speed Test Design Based on Memory Built-in Self-test[J]. 2018, 35(11): 43-46. DOI：

摘要

存储器内建自测试(memory built-in-self-test

MBIST)已成为可测性设计(design-for-testability

DFT)中用以测试嵌入式存储器的重要方法.在一款以太网芯片中基于传统存储器内建自测试

提出了一种多级流水寄存器的全速测试结构

减少了测试时的读写时钟周期

缩短了测试时间

降低了测试成本.经过仿真验证

证明了该流水结构设计能够有效提高内建自测试效率.

Abstract

Memory built-in-self-test has become a major method to test embedded memory in design-for-testability.Based on a traditional memory built-in-self-test in a Ethernet chip

proposes a multistage pipeline stage full-speed test instruction

decrease read and write clock cycle in test

shorten test time

reduce test cost.After simulation verification

it proves the pipeline stage instruction can raise built-in-self-test efficiency.

关键词

Keywords

references

Grawal Vishwani D, Kime Charles R, Saluja Kewal K. A tutorial on built-in self-test, Part 2:applications[J]. IEEE Design % Test of Computer, 1993, 10(2):69-77. DOI: 69

Acharya G P, Rani M A. Survey of test strategies for system-on chip and it's embedded memory[C]// Proc. 2013 IEEE Recent Advances in Intelligent Computational System(RAICS). Trivandrum, India, Trivandrum: IEEE, 2013: 199-204.

Agrawal V D, Kime C R, Saluja K K. A tutorial on built-in-self-test applications[J]. Design % Test of Computers, IEEE, 1993, 10(2):66-77. DOI: 66

徐金荣.基于BIST的嵌入式存储器可测性设计研究[D].北京: 北京交通大学, 2008: 20-23.

Magarshack P. Quality of SoC designs through quality of the design flow: status and needs[C]//Proc. 2nd International Symposium on Quality Electronic Design. Washington, DC CA: IEEE Comput. SoC., 2001: 26-28.

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