A System Design Methodology for High Reliable SoC

LIU Ze-chen; JIANG Jian-fei; WANG Qin; GUAN Ning

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A System Design Methodology for High Reliable SoC

更新时间：2026-09-04

- A System Design Methodology for High Reliable SoC
- Vol. 35, Issue 7, Pages: 54-57(2018)
- 作者机构：
  
  1. 上海交通大学电子信息与电气工程学院,上海,200240
  2. 上海航天电子通讯设备研究所,上海,201108
- 作者简介：
- 基金信息：
- DOI：
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- Published：2018
- 稿件说明：
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柳泽辰, 蒋剑飞, 王琴, 关宁. 一种高可靠SoC芯片的系统级设计方法[J]. 微电子学与计算机, 2018, 35(7): 54-57.

LIU Ze-chen, JIANG Jian-fei, WANG Qin, et al. A System Design Methodology for High Reliable SoC[J]. 2018, 35(7): 54-57.
柳泽辰, 蒋剑飞, 王琴, 关宁. 一种高可靠SoC芯片的系统级设计方法[J]. 微电子学与计算机, 2018, 35(7): 54-57. DOI：

LIU Ze-chen, JIANG Jian-fei, WANG Qin, et al. A System Design Methodology for High Reliable SoC[J]. 2018, 35(7): 54-57. DOI：

摘要

为了实现SoC在系统级的高可靠设计

文本搭建了一个包括PowerPC、DRAM、DMA、SRAM模块的SoC系统级设计平台

并采用VCI总线协议实现互连.针对高可靠性问题

本文提出并实现了三模冗余与ECC纠错编码相结合的存储加固方法

通过一个图像数据处理程序

分析比较了利用冗余和编码带来的可靠性提升.系统级仿真结果表明

本文提出的高可靠设计可以显著提高SoC的可靠性.

Abstract

In this paper

the reliability problem of the SoC is analyzed in system level. In order to implement the high reliable SoC in system level

a SoC system is designed which includes VCI bus

PowerPC processor

DMA controller

SRAM and DRAM interfaces. As for the high reliable SoC

this paper proposed a high reliable storage mechanism based on a TMR and ECC hybrid structure. An image processing program is design to simulate the reliability of the SoC system in system level. The simulation result shows that the proposed high reliable structure can improve the reliability of the SoC system.

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Keywords

references

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赵馨远, 张晓晨, 王亮, 等.晶体管栅形状对单粒子瞬态脉冲特性的影响研究[J].微电子学与计算机, 2014, 31(10):76-80. DOI: 76

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孙铭泽, 郭炜, 周红月, 等.周期精确/位精确的Cache事务级建模方法[J].计算机工程, 2013, 39(8):74-76. DOI: 74

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