A Design of Fully Integrated Alternating Dual Slope ADC

CHENG Tian-yuan; WU Chun-dong; WANG Guo-xing

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A Design of Fully Integrated Alternating Dual Slope ADC

更新时间：2026-09-04

- A Design of Fully Integrated Alternating Dual Slope ADC
- Vol. 35, Issue 10, Pages: 62-66(2018)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
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- Published：2018
- 稿件说明：
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程天元, 吴春东, 王国兴. 一种全集成交替型双积分ADC的设计[J]. 微电子学与计算机, 2018, 35(10): 62-66.

CHENG Tian-yuan, WU Chun-dong, WANG Guo-xing. A Design of Fully Integrated Alternating Dual Slope ADC[J]. 2018, 35(10): 62-66.
程天元, 吴春东, 王国兴. 一种全集成交替型双积分ADC的设计[J]. 微电子学与计算机, 2018, 35(10): 62-66. DOI：

CHENG Tian-yuan, WU Chun-dong, WANG Guo-xing. A Design of Fully Integrated Alternating Dual Slope ADC[J]. 2018, 35(10): 62-66. DOI：

摘要

本文提出了一个应用于生物医学的全集成小面积的交替型双积分模数转换器

将双积分ADC原本单一的积分时间窗口变成多个时间窗口

使正反积分交替进行

极大地减小了积分器所需的RC时间常数

同时节省了大量的面积

有利于实现芯片的全集成.为了消除积分器失调的影响和降低功耗

使用了自动调零结构以及动态比较器.该10 bit双积分ADC在0.35 μm工艺下设计

面积为0.16 mm.在2 V电源电压

418 S/s采样频率下

ADC的功耗为18.5 μA

Matlab仿真结果显示有效位数为9.77 bit.

Abstract

This paper presents a fully on-chip small area dual slope ADC for biomedical application. Base on the proposed multi-window dividing method

the RC time constant of the integrator is greatly reduced

which helps the ADC to save large amount of area for the on-chip capacitor. The auto-zero technique is applied to reduce the offset of integrator

and dynamic comparator is used to save power. The proposed 10 bit dual slope ADC has a sampling rate of 418S/s at 2 V supply voltage

consuming 18.5 μA current. The proposed dual slope ADC is implemented in 0.35 μm CMOS process occupying an area of 0.16 mm. Matlab simulation results show that the effective number of bits (ENOB) for the ADC is 9.77 bit.

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references

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汪正锋, 宁宁, 吴霜毅, 等.一种基于电压窗口技术的超低功耗SAR ADC[J].电子学报, 2014, 44(1): 211-215. DOI: 211

杜微.一种新型高速高分辨率双积分A/D转换器的设计与研究[D].成都: 电子科技大学, 2016.

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