Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization

YE Yun-fei; WU Ning; GE Fen; ZHOU Fang

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Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization

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- Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization
- Vol. 35, Issue 9, Pages: 52-54(2018)
- 作者机构：
  
  1. 南京航空航天大学电子信息工程学院,江苏,南京,210016
  2. 南京铁道职业技术学院机构创新学院,江苏,南京,210031
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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叶云飞, 吴宁, 葛芬, 周芳. 一种适用于三维芯片间时钟同步的全数字延时锁定环设计[J]. 微电子学与计算机, 2018, 35(9): 52-54.

YE Yun-fei, WU Ning, GE Fen, et al. Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization[J]. 2018, 35(9): 52-54.
叶云飞, 吴宁, 葛芬, 周芳. 一种适用于三维芯片间时钟同步的全数字延时锁定环设计[J]. 微电子学与计算机, 2018, 35(9): 52-54. DOI：

YE Yun-fei, WU Ning, GE Fen, et al. Design of ADDLL for 3D-IC Die-to-Die Clock Synchronization[J]. 2018, 35(9): 52-54. DOI：

摘要

本文提出了一种适用于三维集成电路芯片间时钟同步的全数字延时锁定环设计.在给定的三维集成电路中

该全数字延时锁定环采用可变逐次逼近寄存器控制器设计来缩短锁定时间

以消除谐波锁定问题并拓宽工作频率范围

实现硅过孔引起的延时偏差可容忍和垂直堆叠芯片间时钟信号同步.整个设计采用TSMC 65 nm CMOS低功耗工艺实现.仿真结果显示在工艺角最坏情况下最高工作频率是833 MHz(SS

125℃

1.08 V)

在工艺角最好情况下最低工作频率是167 MHz(FF

-40℃

1.32 V)

整个工作频率范围内最长锁定时间固定为103个输入时钟周期

在典型工艺角下功耗为0.8mW@833 MHz(TT

25℃

1.2 V).版图有效核心面积为0.018 mm.

Abstract

In this paper

an all-digital delay-locked loop (ADDLL) for die-to-die clock synchronization of three-dimensional integrated circuit (3D-IC) is presented. The proposed ADDLL can endure the delay variations between through silicon vias and synchronize the clock signals between vertically stacked dies of the given 3D-IC. In order to solve the harmonic lock problem and widen the operating frequency

the circuit shortened the lock process by the use of variable successive approximation register-controlled scheme. The presented ADDLL is implemented using the TSMC 65 nm CMOS low power technology

and the simulation results show that the highest operating frequency is 833 MHz at the worst case (SS

125℃

1.08 V)

the lowest operating frequency is 167 MHz at the best case (FF

-40℃

1.32 V)

the longest lock time is 103 cycles of the input clock

and the power consumption is estimated to be 0.8mW@833MHz at the typical case (TT

25℃

1.2 V). The area of the ADDLL per die is 0.018 mm.

关键词

Keywords

references

Chung C C, Hou C Y. All-digital delay-locked loop for 3D-IC die-to-die clock synchronization[C]// International Symposium on VLSI Design, Automation and Test. IEEE, Hsinchu, China, 2014: 1-4.

Yang R J, Liu S I. A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm[J]. IEEE Journal of Solid-State Circuits, 2007, 42(2):361-373. DOI: 361

Dehng G K, Hsu J M, Yang C Y, et al. Clock-deskew buffer using a SAR-controlled delay-locked loop[J]. IEEE Journal of Solid-State Circuits, 2000, 35(8):1128-1136. DOI: 1128

Wang J S, Chien Y C, Lin J H, et al. ADDLL/VDD-biasing codesign for process characterization, performance calibration, and clock synchronization in variation-tolerant designs[C]// IEEE International Conference on ASIC. Xiamen, China, IEEE, 2011: 47-50.

Kim D H, Athikulwongse K, Lim S K. Study of through-silicon-via impact on the 3D stacked IC layout[J]. IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(5):862-874. DOI: 862

Song T, Lim S K. Die-to-Die parasitic extraction targeting face-to-face bonded 3D ICs[J]. Journal of Information % Communication Convergence Engineering, 2015, 13(3):172-179. DOI: 172

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