Design of Approximate Booth Multipliers for Error-Tolerant Computing

CAO Tian; LIU Wei-qiang; ZHU Yu-ying

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Design of Approximate Booth Multipliers for Error-Tolerant Computing

更新时间：2026-09-04

- Design of Approximate Booth Multipliers for Error-Tolerant Computing
- Vol. 35, Issue 7, Pages: 67-71(2018)
- 作者机构：
  
  南京航空航天大学电子信息工程学院,江苏,南京,210016
- 作者简介：
- 基金信息：
- DOI：
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- Published：2018
- 稿件说明：
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操天, 刘伟强, 朱玉莹. 面向可容错计算的近似Booth乘法器设计[J]. 微电子学与计算机, 2018, 35(7): 67-71.

CAO Tian, LIU Wei-qiang, ZHU Yu-ying. Design of Approximate Booth Multipliers for Error-Tolerant Computing[J]. 2018, 35(7): 67-71.
操天, 刘伟强, 朱玉莹. 面向可容错计算的近似Booth乘法器设计[J]. 微电子学与计算机, 2018, 35(7): 67-71. DOI：

CAO Tian, LIU Wei-qiang, ZHU Yu-ying. Design of Approximate Booth Multipliers for Error-Tolerant Computing[J]. 2018, 35(7): 67-71. DOI：

摘要

本文提出了一种通过近似因子来实现精度可调的近似Booth乘法器的设计方法

并利用归一化的平均误差距离及功耗延时的乘积来评估近似乘法器的可靠性与硬件复杂度.综合考虑可靠性与硬件复杂度

本文所设计的近似乘法器与已有设计方案相比性能更优

并在图像处理等可容错计算应用中显示出较好的应用价值.

Abstract

This paper proposes the approximate Booth multipliers whose accuracy can be adjusted by changing the so called approximate factor. The reliability and hardware complexity of the proposed multiplier are evaluated by the normalized mean error distance (NMED) and power-delay product (PDP). Considering both the reliability and hardware complexity

the proposed designs are better than the existing approximate Booth multipliers. Case studies into image processing show the validity of the proposed approximate multipliers.

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references

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Jiang H, Han J, Qiao F. Approximate radix-8 booth multipliers for low-power and high-performance operation[J]. IEEE Transactions on Computers, 2016, 65 (8) :2638-2644. DOI: 2638

Momeni A, Han J, Montuschi P, et al. Design and analysis of approximate compressors for multiplication[J]. IEEE Transactions on Computers, 2015, 64(4): 984-994. DOI: 984

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崔晓平, 高鹏辉, 尹洁珺, 等. 54位高速冗余二进制乘法器的设计[J].微电子学与计算机, 2014, 31(4):140-143. DOI: 140

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