Diagonal-Based for TSV Fault Tolerance Design

LIU Jun; Dong Peng; REN Fu-ji

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Diagonal-Based for TSV Fault Tolerance Design

更新时间：2026-09-04

- Diagonal-Based for TSV Fault Tolerance Design
- Vol. 35, Issue 11, Pages: 73-78(2018)
- 作者机构：
  
  1. 合肥工业大学计算机与信息学院,安徽,合肥,230009
  2. 合肥工业大学情感计算与先进智能机器安徽省重点实验室机构,安徽,合肥,230009
  3. 日本德岛大学先端技术科学教育部, 日本德岛 7708502
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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刘军, 董鹏, 任福继. 基于对角线的硅通孔容错设计[J]. 微电子学与计算机, 2018, 35(11): 73-78.

LIU Jun, Dong Peng, REN Fu-ji. Diagonal-Based for TSV Fault Tolerance Design[J]. 2018, 35(11): 73-78.
刘军, 董鹏, 任福继. 基于对角线的硅通孔容错设计[J]. 微电子学与计算机, 2018, 35(11): 73-78. DOI：

LIU Jun, Dong Peng, REN Fu-ji. Diagonal-Based for TSV Fault Tolerance Design[J]. 2018, 35(11): 73-78. DOI：

摘要

三维集成电路通过使用硅通孔(through-silicon vias

TSV)作为垂直方向上芯片的通信链路

具有高密度

高带宽

低功耗等优点.由于TSV在制造和使用过程中可能会出现故障

导致整个三维芯片的故障.为了提高三维芯片的良品率

TSV的良品率必须尽可能的提高.本文提出了一种新的基于对角线的TSV容错方案

并提出了基于最大流算法的故障修复算法

在TSV出现故障时使用对角线中的冗余TSV来修复故障TSV以提高整个三维芯片的良品率.实验结果表明

相比基于路由的容错方案

本文提出的基于对角线的TSV容错方案

芯片修复率可以达到98.38%至98.96%

方案造成的面积开销降低了70%左右。

Abstract

Three dimensional integrated circuits

using through-silicon vias(TSVs) as the communication link between vertical chip

with the advantages of high density

high bandwidth and low power consumption. As the TSV during processing and using process may be failure

will lead to the entire three-dimensional chip failure. In order to improve the yield of 3D chips

the yield of TSV must be raised as much as possible. This paper presents a novel diagonal-based redundant TSV repair scheme and proposes a repair algorithm based on maximum flow algorithm to tolerance the faulty TSV with redundant TSVs in the diagonal to improve the yield of the entire three-dimensional chip. Experimental results show that the yield of the proposed repair strategy is 98.38% to 98.96% and the hardware overhead can be reduced by up to 70% compared to router-based technique.

关键词

Keywords

references

Shengcheng Wang, Mehdi B, Tahooriand Krishnendu Chakrabarty. Defect clustering-aware spare-TSV allocationfor 3DICs[D]. Duke University, Durham, USA, 2015: 307-314.

Goldberg A V, Rao S. Beyond the flow decomposition barrier[J]. Journal of the ACM, 1998, 45(5):783-797. DOI: 783

Marinissen E J, Zorian Y. Testing 3D chips containing throughsilicon vias[C]//Proc. IEEE Int'l Test Conf. Austin, 2009: 1-11.

Shijie Zhang, Xiaole Cui, Qiang Zhang, et al. ATSV repair method for clutered faults[J]. High Voltage Apparatus, 2011, 47 (12) :96-99. DOI: 96

Jiang L, XU Q, Eklow B. On effective TSVs repair for 3D-stacked ICs[J]. IEEE/ACM Proc. Design, Automation, and Test in Europe, 2011, 58(11):1-10. DOI: 1

刘军, 李进, 王伟.基于相邻多层冗余共享的三维存储器堆叠方法[J].微电子学与计算机, 2017, 34(7):1-6. DOI: 1

Zhang Ling, Wang Weizheng, Mei Junjin. Fault-tolerant design for TSVs of 3D stacked ICs[J]. Computer Engi-neering and Applications, 2015, 51(14):11-16. DOI: 11

孟真, 张兴成, 刘谋. TSV封装中互连结构的差分串扰建模研究[J].微电子学与计算机, 2017, 34(9):1-6. DOI: 1

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