Parallel Acceleration Design of Convolutional Neural Network Based on FPGA

LIU Zhi-cheng; ZHU Yong-xin; WANG Hui; TIAN Li; FENG Song-lin

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Parallel Acceleration Design of Convolutional Neural Network Based on FPGA

更新时间：2026-09-04

- Parallel Acceleration Design of Convolutional Neural Network Based on FPGA
- Vol. 35, Issue 10, Pages: 80-84(2018)
- 作者机构：
  
  1. 中国科学院机构上海高等研究院CMOS图像传感器实验室,上海,201210
  2. 中国科学院大学机构,北京,101408
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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刘志成, 祝永新, 汪辉, 田犁, 封松林. 基于FPGA的卷积神经网络并行加速结构设计[J]. 微电子学与计算机, 2018, 35(10): 80-84.

LIU Zhi-cheng, ZHU Yong-xin, WANG Hui, et al. Parallel Acceleration Design of Convolutional Neural Network Based on FPGA[J]. 2018, 35(10): 80-84.
刘志成, 祝永新, 汪辉, 田犁, 封松林. 基于FPGA的卷积神经网络并行加速结构设计[J]. 微电子学与计算机, 2018, 35(10): 80-84. DOI：

LIU Zhi-cheng, ZHU Yong-xin, WANG Hui, et al. Parallel Acceleration Design of Convolutional Neural Network Based on FPGA[J]. 2018, 35(10): 80-84. DOI：

摘要

本文根据卷积神经网络特点

提出了一种基于FPGA的流水线并行加速方案

设计优化了卷积模块电路、激活模块电路以及下采样模块电路

从而构建了卷积神经网络运算的FPGA基本单元.在网络结构和处理数据相同的情况下

50 MHz频率的FPGA计算效率为CPU的8倍、GPU的近5倍

而功耗则只占GPU的27.8%.

Abstract

Sccording to the characteristics of convolutional neural network

this paper proposes a pipeline parallel acceleration scheme of FPGA. Convolution module circuit

activation module circuit and down-sampling module circuit are designed to construct the FPGA basic unit of convolution neural network operation. With the same network structure and processing data

FPGAs with 50 MHz frequency are 8x and nearly 5x computational efficiency of the CPU and the GPU

while power consuming only 27.8% of the GPU.

关键词

Keywords

references

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