ASIC Implementation of Digital Down Converter Built in 4 GS/s-12 bit ADC

XUE Jin-xin; MA Chong-he; ZHOU Lei; WU Dan-yu; WU Jin

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ASIC Implementation of Digital Down Converter Built in 4 GS/s-12 bit ADC

更新时间：2026-09-04

- ASIC Implementation of Digital Down Converter Built in 4 GS/s-12 bit ADC
- Vol. 36, Issue 1, Pages: 85-89(2019)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,101408
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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薛金鑫, 马崇鹤, 周磊, 吴旦昱, 武锦. 4GS/s-12bit ADC内置数字下变频器[J]. 微电子学与计算机, 2019, 36(1): 85-89.

XUE Jin-xin, MA Chong-he, ZHOU Lei, et al. ASIC Implementation of Digital Down Converter Built in 4 GS/s-12 bit ADC[J]. 2019, 36(1): 85-89.
薛金鑫, 马崇鹤, 周磊, 吴旦昱, 武锦. 4GS/s-12bit ADC内置数字下变频器[J]. 微电子学与计算机, 2019, 36(1): 85-89. DOI：

XUE Jin-xin, MA Chong-he, ZHOU Lei, et al. ASIC Implementation of Digital Down Converter Built in 4 GS/s-12 bit ADC[J]. 2019, 36(1): 85-89. DOI：

摘要

本文提出了一种适合ASIC实现的可编程的数字下变频器(DDC)设计方法

该DDC嵌入于4GS/s-12bit ADC中

能够处理频率为4GHz的输入信号

并提供抽取因子分别为4、8、16、32的降采样功能.设计的DDC由一个基于CORDIC算法实现的数控振荡器(NCO)和一个全半带滤波器(HB-FIR)级联结构的抽取滤波器组组成.优化半带滤波器系数和各级数据精度

提出多种改进结构优化设计

有效减少硬件开销.基于40 nm CMOS工艺

完成数字下变频器的前端设计和后端实现

并进行了流片.仿真结果显示

该设计可以在500 MHz的工作时钟频率下达到设计目标

抽取因子为4模式下

最大无衰减通带带宽可达420 MHz

版图面积1550*650 μm

0.9 V工作电压

功耗为180.69 mW.验证了该设计方法适合于高速高精度数字信号的2n下变频.

Abstract

This paper proposes a programmable digital downconverter (DDC) design method for ASIC implementation. The DDC is embedded in a 4GS/s-12bit ADC and is capable of processing input signals at a frequency of 4GHz and provides extraction factors of 4 Downsampling function for 8

16 and 32. The designed DDC consists of a numerically controlled oscillator based on the CORDIC algorithm and a decimation filter bank implemented by a full HB-FIR filter. According to the HB-FIR filter coefficient characteristics and spectral response characteristics

a variety of improved structural optimization designs are proposed in hardware implementation

reducing the area by about 50%. Based on the 40nm CMOS process

digital front-end and back-end implementations of the digital downconverter were completed and taped out. The simulation results show that the design can achieve the design goals at a working clock frequency of 500 MHz. The layout area is 1550*650um^2

and the operating voltage is 0.9 V. The power consumption is 180.69 mW. It is verified that the design method is suitable for 2^n down conversion of high-speed and high-precision digital signals.

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references

Hanyu Wang, Jinxiang Wang, Fangfa Fu. An efficient low-cost fixed-point digital down converter with modified filter bank[C]//2013 IEEE 10th International Conference on ASIC(ASICON 2013). Shenzhen, China, 2013.

Rashmi M Mani, Abdul Imran Rasheed. Design and implementation of WDF for digital down converter on FPGA for LTE application[C]//2014 International Conference on Advances in Electronics, Computers and Communications(ICAECC).[S.l].2014

Sudhir Rao Rupanagudi, Chandrika B V. Design of a low power digital down converter for 802.16m-4G WIMAX on FPGA[C]//International Conference on Advances in Computing, Kollam, Kerala, India, IEEE, 2014: 2303-2308

Zhao Kongrui, Zhang Chao. A polyphase digital down converter method for GHz high speed sampling signal[C]//2015 IEEE 12th International Conference on Electronic Measurement % Instruments. Honolulu, Hawaii, USA, 2015: 907-910

Zhuo Zhihai, Li Shange, Zhang Zechao. Implementation of high-performance multi-structure digital down converter based on FPGA[C]//ICSP2012 Proceedings. Beijing, China, 2012: 31-35.

李飞.数字控制振荡器(NCO)的FPGA实现[J].电子元器件应用, 2010, 11(11): 42-44 DOI: 42

张尊, 李绍荣.基于改进的CORDIC算法的NCO实现[J].信息通信, 2009, 22(4):11-13 DOI: 11

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