System Level Power Modeling for Course-Grained Reconfigurable Processor

MU Chang-gen; ZHAO Zhong-yuan; SHENG Wei-guang; MAO Zhi-gang

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System Level Power Modeling for Course-Grained Reconfigurable Processor

更新时间：2026-09-04

- System Level Power Modeling for Course-Grained Reconfigurable Processor
- Vol. 35, Issue 9, Pages: 70-73(2018)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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穆昌根, 赵仲元, 绳伟光, 毛志刚. 粗粒度可重构处理器的系统级功耗建模[J]. 微电子学与计算机, 2018, 35(9): 70-73, 78.

MU Chang-gen, ZHAO Zhong-yuan, SHENG Wei-guang, et al. System Level Power Modeling for Course-Grained Reconfigurable Processor[J]. 2018, 35(9): 70-73.
穆昌根, 赵仲元, 绳伟光, 毛志刚. 粗粒度可重构处理器的系统级功耗建模[J]. 微电子学与计算机, 2018, 35(9): 70-73, 78. DOI：

MU Chang-gen, ZHAO Zhong-yuan, SHENG Wei-guang, et al. System Level Power Modeling for Course-Grained Reconfigurable Processor[J]. 2018, 35(9): 70-73. DOI：

摘要

本文针对粗粒度可重构结构

提出一种可根据不同结构参数进行拓展的系统级功耗建模方法.该方法采用层次描述的方法

分别从体系结构、电路和工艺层建立功耗模型

再利用线性模型计算出系统的整体功耗.对比仿真和实测数据的误差

验证了该建模方法的有效性.在探索粗粒度可重构架构的早期

可以应用该方法来评估可重构处理器的功耗.

Abstract

In this paper

we propose a system-level power modeling method that can be extended according to different structural parameters for coarse-grained reconfigurable architecture. The method described by the level of methods

respectively

from the architecture

circuit and technology level to establish the power model

and then use the linear model to calculate the overall power consumption of the system. Contrasting the errors of simulation and measured data

the validity of this modeling method is verified. Early in exploring coarse-grained reconfigurable architectures

this approach can be applied to evaluate the power consumption of reconfigurable processors.

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references

Guthaus T, R Ringenberg M, Ernst J S, et al. MiBench: a free, commercially representative embedded benchmark suite[C]//IEEE International Workshop on Workload Characterization.[s.l.]. 2001: 3-14.

Mukherjee R, Mondal S, Memik S O. Thermal sensor allocation and placement for reconfigurable systems[C]//Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design. Washington, USA, 2006: 437-442.

USA Weste N, Harris D. CMOS VLSI design: a circuits and systems perspective[M]. 3rd ed. USA: New Jersey, Addison Wesley, 2004.

Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, et al. Resource-saving compile flow for coarse-grained reconfigurable architectures[C]//ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. Riviera Maya, Mexico, 2015.

Sheng Li, Jung Ho Ahn, Richard D, et al. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures[C]//Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on. New York, NY, USA, 2009.

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