Large FFT is widely applied to high throughput and high real-time applications such as image processing
radar signal processing
satellite communications and biomedicine. At the same time
the development of multi-core system has been the mainstream in the past few years. So it is valuable to study the implementation of large FFT on the multi-core systems which is high efficient and low resource consumption Extremely. This paper presents one implementation of large FFT on homogeneous multi-core system and achieves a good balance between the on-chip memory consumption and the payload in the process elements (PE). This paper adopts the 2-diamension FFT principle and radix-2 decimation-in-time (DIT) FFT method
which divides the large FFT into several shorter ones and computes each part with the process elements (PE) on the homogeneous multi-core system. In order to reduce the time of processor execution and reduce programming tasks
this paper make the source data and the results of data of each butterfly access to the same storage area skillfully. In addition
a pipeline structure is introduced for multiple FFTs computing at the same time aiming at improving the parallelism.
关键词
Keywords
references
Andor Krizsan, Dr. Daniela Volke, Stefanie Weinert, et al. Generator of dynamically reconfigurable processor[J]. Artificial Life and Robotics, 2015, 20(2):103-108. DOI: 103
Ilija M. Miĺičic;, Djordje Ladjinovic. Computer simulation of two frequency response excitation 1D dynamic model using FFT and IFFT algorithm[C]// International Conference - Contemporary Achievements in Civil Engineering. 2016.
Ingemarsson C, Källström P, Qureshi F, et al. Efficient FPGA Mapping of Pipeline SDF FFT Cores[J]. IEEE Transactions on Very Large Scale Integration Systems, 2017(99):1-12. DOI: 1
Qureshi I A, Qureshi F. Generalized twiddle factor index mapping of radix-2 fast Fourier transform algorithm[C]// IEEE International Conference on Software Engineering and Service Science. IEEE, 2014.
Friedrich J, Le H, Starke W, et al. The POWER8 TM, processor: Designed for big data, analytics, and cloud environments[C]// IEEE International Conference on Ic Design % Technology. IEEE, 2014: 1-4.
Liang C, Huang X. Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture[C]// IEEE International Conference on Application-Specific Systems. Architectures and Processors. IEEE, 2009, 231-234.
Schmittfull M, Vlah Z. FFT-PT: Reducing the 2-loop large-scale structure power spectrum to one-dimensional, radial integrals[J]. Physical Review D, 2016, 94(10).