In order to suppress the quantization noise caused by the Delta-sigma modulator (DSM) and reduce the clock jitter of the fractional-N clock source

a novel jitter reduction technique based on cascaded Phase-Lock Loops (PLL) is proposed. By multiplying the frequency of the first stage to increase the operating frequency of the DSM

the quantization noise is suppressed. Meanwhile

for the difficulties of phase conversion caused by the high-frequency reference

a high-speed charge pump is proposed in this paper

which realizes the dynamic matching of the current without increasing the power consumption. The prototype of the cascaded PLL is implemented on the 180 nm CMOS process and the simulation results show that the output frequency range is 3~4 G

with 137 fs jitter performance and the total power consumption is 47.7mW.