An Application Design Fault of Antifuse FPGA

DU Tao; XU Bai-chuan; LI Wei; CAO Xing; WU Fang-min

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An Application Design Fault of Antifuse FPGA

更新时间：2026-09-04

- An Application Design Fault of Antifuse FPGA
- Vol. 35, Issue 9, Pages: 108-112(2018)
- 作者机构：
  
  电子科技大学电子薄膜与集成器件国家重点实验室机构,四川,成都,610054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2018
- 稿件说明：
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杜涛, 许百川, 李威, 晁醒, 吴方明. 一种反熔丝FPGA应用设计故障[J]. 微电子学与计算机, 2018, 35(9): 108-112, 117.

DU Tao, XU Bai-chuan, LI Wei, et al. An Application Design Fault of Antifuse FPGA[J]. 2018, 35(9): 108-112.
杜涛, 许百川, 李威, 晁醒, 吴方明. 一种反熔丝FPGA应用设计故障[J]. 微电子学与计算机, 2018, 35(9): 108-112, 117. DOI：

DU Tao, XU Bai-chuan, LI Wei, et al. An Application Design Fault of Antifuse FPGA[J]. 2018, 35(9): 108-112. DOI：

摘要

由于反熔丝FPGA架构和实现原理的特殊性

反熔丝FPGA应用设计在物理实现时

存在一种易于发生、故障现象不稳定且具有一定隐蔽性的时序逻辑故障.通过对故障现象、诱因、原理的深入剖析

发现该应用设计故障与反熔丝FPGA的散出能力限制(Fanout limit)关联

并有针对性地提出了根除故障因素的解决方案.通过实测验证表明

本解决方案能有效消除该类应用设计故障.

Abstract

Due to the particularity of the architecture and implementation principle of the antifuse FPGA

there is a kind of sequential logic fault which is prone to occur

unstable in the fault phenomenon and has a certain concealment when the application design is implemented in the antifuse FPGA. Through in-depth analysis of the fault phenomenon

causes and principles

it is found that the application design fault is related to the drive capability (Fanout limit) of the antifuse FPGA. Aiming at the fault characteristics

a set of solutions to eradicate the fault factors are proposed. The experimental results show that the solutions can effectively eliminate the application design fault.

关键词

Keywords

references

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