Design of a 25 Gbps multi-channel MZM driver

ZONG Cheng; JI Peng-fei; HE Wei-feng

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Design of a 25 Gbps multi-channel MZM driver

更新时间：2026-09-04

- Design of a 25 Gbps multi-channel MZM driver
- Vol. 36, Issue 8, Pages: 1-5(2019)
- 作者机构：
  
  上海交通大学微纳电子系,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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宗诚, 纪鹏飞, 何卫锋. 25 Gbps多通道MZM驱动器设计[J]. 微电子学与计算机, 2019, 36(8): 1-5.

ZONG Cheng, JI Peng-fei, HE Wei-feng. Design of a 25 Gbps multi-channel MZM driver[J]. 2019, 36(8): 1-5.
宗诚, 纪鹏飞, 何卫锋. 25 Gbps多通道MZM驱动器设计[J]. 微电子学与计算机, 2019, 36(8): 1-5. DOI：

ZONG Cheng, JI Peng-fei, HE Wei-feng. Design of a 25 Gbps multi-channel MZM driver[J]. 2019, 36(8): 1-5. DOI：

摘要

本文提出了一种面向高密度集成的多通道Mach-Zehnder调制器的驱动器电路结构

单通道驱动器包含信号均衡器、时钟树模块、时钟延时控制模块和输出摆幅控制模块等电路

支持各通道25 GHz高速差分时钟延时与驱动器输出摆幅的独立可调

以及最高25 Gbps的NRZ数字信号传输.基于TowerJazz0.18 μm SiGe BiCMOS工艺

完成了6通道驱动器的芯片设计.仿真结果表明

单通道带宽达到17.2 GHz

最大差分输出摆幅为3 Vppd

Jitter约为8.9 ps

在2.3/3.6V双电源供电下单通道功耗约为646.9 mW.

Abstract

A design of multi-channel Mach-Zehnder modulator driver aiming at high-density integration is proposed in this paper

the single-channel circuits consists of signal equalizer

clock tree

delay control module

output swing control module and other amplifying components

supporting delay-tunable 25GHz high-speed differential clock signals

swing-tunable differential outputs

and up to 25 Gbps NRZ digital signal transmission. Based on TowerJazz 0.18 μm SiGe BiCMOS technology

the driver chip consists of 6 individual channels

with a bandwidth of 17.2 GHz

a maximum output swing of 3Vppd and an jitter of 8.9 ps. The chip consumes 646.9 mW from a dual power supply of 2.3/3.6V.

关键词

Keywords

references

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CISCO. Cisco Global Cloud Index: Forecast and Methodology2016-2021 White Paper [R]. USA: Cisco, 2018.

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ALI GHIASI.Large data centers interconnect bottlenecks [J]. Opt. Express, 2015, 23(3): 2085-2090. DOI: 2085

KUMAR R D, MADHUSOOTHANAN K N, NAIR K R S, et al. A simple cost effective laser driving mechanism for optical communication [C]. 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI). Chennai: 2017: 433-435.

TANAKA S, TAKASI S, TSUYOSHI A. Ultra-low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver [J]. Journal of Lightwave Technology, 2018, 36(5):1275-1280. DOI: 1275

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