Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol

YANG Chao-xiang; KONG Xian-wei; LUAN Wen-huan; ZHANG Yuan-hang; WANG Zhi-jun; ZHANG Chun; WANG Zi-qiang

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Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol

更新时间：2026-09-04

- Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol
- Vol. 36, Issue 3, Pages: 7-11(2019)
- 作者机构：
  
  1. 清华大学微电子学研究所,北京,100084
  2. 中国电子技术标准化研究院集成电路测试与评价工业和信息化部重点实验室,北京,100176
- 作者简介：
- 基金信息：
- DOI：
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- Published：2019
- 稿件说明：
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杨钞翔, 孔宪伟, 栾文焕, 张远航, 王志军, 张春, 王自强. 基于FC协议的PCS层设计和协议分析仪验证[J]. 微电子学与计算机, 2019, 36(3): 7-11.

YANG Chao-xiang, KONG Xian-wei, LUAN Wen-huan, et al. Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol[J]. 2019, 36(3): 7-11.
杨钞翔, 孔宪伟, 栾文焕, 张远航, 王志军, 张春, 王自强. 基于FC协议的PCS层设计和协议分析仪验证[J]. 微电子学与计算机, 2019, 36(3): 7-11. DOI：

YANG Chao-xiang, KONG Xian-wei, LUAN Wen-huan, et al. Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol[J]. 2019, 36(3): 7-11. DOI：

摘要

FC光纤通道协议作为新一代重要总线技术

具有带宽高、扩展性强、可靠性强、实时性强、支持多种媒介、抗电磁干扰等优良特点

发展迅速并在诸多领域得到了广泛应用.本文针对FC协议的PCS层进行深入研究

解析其关键模块:弹性缓冲器、8B/10B编解码器、位宽变换器、同步器等

提出整体设计架构

使用verilog语言完成代码设计

搭建回环验证平台

并采用FC专用协议分析仪

结合FPGA进行验证

完成设计.

Abstract

As an important new generation of bus technology

the Fibre Channel protocol has the excellent features of high bandwidth

strong scalability

high reliability

real-time performance

supporting for multiple media

and immunity to electromagnetic interference. It has developed rapidly and has been widely used in many fields. This article carries on the thorough research to the PCS layer of the FC protocol

and analyzes its key modules: elastic buffer

8B/10B codec

bit-width converter

synchronizer

etc. And it proposes an overall design architecture

uses verilog language to complete code design

builds a loopback verification platform

and uses the FC protocol analyzer

combined with FPGA verification to complete the design.

关键词

Keywords

references

VERILOG E, CUMMINGS C E. Simulation and synthesis techniques for asynchronous FIFO design[J]. Snug, 2002, Section TB2(3):1-18. DOI: 1

林强, 熊华钢, 张其善.光纤通道综述[J].计算机应用研究, 2006, 23(2):9-13. DOI: 9

杜玲, 廖小海.FC-AE-1553总线在箭载测量系统中应用研究[J].遥测遥控, 2015, 39(5):33-43. DOI: 33

SUN G C, YU D S. Design of dual-gigabit tran- sceiver for fibre channel FC-1 layer[C]//Electron Devices and Solid-State Circuits, EDSSC 2008. IEEE International Conference, China, Hongkong, 2008: 1-4.

KIM Y W, KANG J K. An 8B/10B encoder with a modified coding table[C]//Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference. Macao, China, 2008: 1522-1525.

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