BAI Lian-long, Masao Kuriyama, HE Hong-kai. A read reference generator with negative temperature coefficient for 3D NAND flash memory[J]. 2019, 36(7): 12-16.
BAI Lian-long, Masao Kuriyama, HE Hong-kai. A read reference generator with negative temperature coefficient for 3D NAND flash memory[J]. 2019, 36(7): 12-16.DOI:
A read reference generator with negative temperature coefficient for 3D NAND flash memory
本文提出了一种具有负温度系数的读电压基准发生器来补偿阈值电压随温度的变化.本文所提出的具有负温度系数的电压电路通过分别调整负温度系数(complementary to absolute temperature
CTAT)电流和零温度系数(zero to absolute temperature
ZTAT)电流
可输出具有相同负温度系数的不同大小的读电压
并通过调制器(regulator)来提高其输出电压的范围.结果表明
所提出的方法可以提供一个可配置的读电压范围为1.5~4.5 V.
Abstract
3D NAND flash reliability is vulnerable to temperature variation due to the threshold voltages () shift
which will further deteriorate the read margin. To solve this issue
a read reference generator with negative temperature coefficient was proposed to compensate the shift under the changes of temperature. The proposed generator outputs different level voltages with the same negative temperature coefficient by adjusting the CTAT (complementary to absolute temperature) current and ZTAT (zero to absolute temperature) current
respectively. And the regulator was used to enhance the range of output voltage. The results showed the proposed method could provide a configurable range of read voltage of 1.5~4.5 V.
关键词
Keywords
references
CAI Y, LUO Y, HARATSCH E F, et al. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery [C]// IEEE, Inter- national Symposium on High PERFORMANCE Computer Architecture. New Orleans, USA, IEEE, 2015: 551-563.
TANZAWA T, TANAKA T, TAMADA S, et al. A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories[C]// ESSCIRC 2010.[S.L.], IEEE, 2010: 106-109.
MIYAJI K, JOHGUCHI K, HIGUCHI K, et al. An integrated variable positive/negative temperature coefficient read reference generator for MLC PCM/NAND Hybrid 3D SSD[C]// Solid State Circuits Conference. Singapore, IEEE, 2013: 313-316.
王超.一个快速瞬态响应无片外电容LDO设计[D].广州: 华南理工大学, 2018.
CHOI S W, PARK K T, PASSERINI M, et al. A cell current compensation scheme for 3D NAND FLASH memory[C]// Solid-State Circuits Conference. Lausanne, Switzerland, IEEE, 2016: 1-4.
Berlin MICHELONI R, CRIPPA L, MARELLI A. Inside NAND Flash Memories[M]. Berlin: Springer Netherlands, 2010.
CAI Y, HARATSCH E F, MUTLU O, et al. Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling[C]// Design, Automation % Test in Europe Conference % Exhibition. Grenoble, France, IEEE, 2013: 1285-1290.
KLECZEK R, GRYBOS P. Low voltage area efficient current-mode CMOS bandgap reference in deep submicron technology[C]// Mixed Design of Integrated Circuits % Systems. Lublin, Poland. IEEE, 2014: 247-251.