Design and implementation of a pipeline primitives assembly circuit

PEI Xi-jie; TIAN Ze; ZHENG Xi-jian; ZHANG Jun; XU Hong-jie; LIU Ning-ning

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Design and implementation of a pipeline primitives assembly circuit

更新时间：2026-09-04

- Design and implementation of a pipeline primitives assembly circuit
- Vol. 36, Issue 8, Pages: 10-13(2019)
- 作者机构：
  
  1. 中国航空工业集团西安航空计算技术研究所,陕西,西安,710068
  2. 集成电路与微系统设计航空科技重点实验室,陕西,西安,710068
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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裴希杰, 田泽, 郑新建, 张骏, 许宏杰, 刘宁宁. 一种流水处理图元建立电路的设计与实现[J]. 微电子学与计算机, 2019, 36(8): 10-13, 18.

PEI Xi-jie, TIAN Ze, ZHENG Xi-jian, et al. Design and implementation of a pipeline primitives assembly circuit[J]. 2019, 36(8): 10-13.
裴希杰, 田泽, 郑新建, 张骏, 许宏杰, 刘宁宁. 一种流水处理图元建立电路的设计与实现[J]. 微电子学与计算机, 2019, 36(8): 10-13, 18. DOI：

PEI Xi-jie, TIAN Ze, ZHENG Xi-jian, et al. Design and implementation of a pipeline primitives assembly circuit[J]. 2019, 36(8): 10-13. DOI：

摘要

为了提高图形处理器的图形绘制能力

本文设计了一种能够流水处理的图元建立电路

实现了OpenGL定义的9种图元到点、线和三角形简单图形的转换

可有效降低图形流水线后续单元任务的复杂度

提高图形绘制性能.通过虚拟仿真和FPGA原型验证确认

实现了基本图元的建立功能

频率能够达到400 MHz以上

三角形建立峰值可达380 M/s.

Abstract

Primitives is a basic unit for graphic processing. To improve the performance for GPUs a primitive assembling circuit is presented. The circuit has a simple structure

pipelining and can convert all primitivesdefined by OpenGL to separate point

line or triangle. The circuit can reduce the complexity of the flowing unit task and improve the performance of drawing. The verification of the circuit is completed by module level simulation verification and FPGA prototype verification

the results show that the design is function and the frequency can reach 400MHz and the peak value of triangle assembly can reach 380M/s.

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references

章元智.嵌入式GPU设计与实现[D].山东: 山东大学, 2014.

韩伟.图形处理芯片的研究与设计验证[D].上海: 上海交通大学. 2008

Xilinx. Vivado Design Suite User Guide Using Constraints UG903 [S]. America: Xilinx, 2017.

饶志恒.图形处理器图形管线的研究与实现[D].长沙: 湖南大学, 2011.

OWENS J D, LUEBKE D, GOVINDARAJU NETAL. A survey of general-purpose computation on graphics hardware[J]. Computer Graphics Forum, 2007, 26(1) : 80-113. DOI: 80

谭显强.基于FPGA的3D图形处理器IP核的设计与实现[D].南京: 南京航空航天大学, 2010.

张淮声, 余莉.一种三维绘制中可编程的图元设置着色方法[J].集成电路应用. 2017, 34(6) : 9-13. DOI: 9

QIAO L F. Verilog HDL Digital system design and verification[J]. Electronic Industry Press, 2009(4) : 134-146. DOI: 134

邓艺, 田泽, 韩立敏.一种负载均衡的3D引擎任务调度策略[J].电子技术与应用, 2017, 43(5) : 55-59. DOI: 55

李攀, 田文娟, 李娟, 等.FC协议处理芯片设计与实现[J].电子技术与应用, 2016, 42(9), 147-151. DOI: 147

黎小玉, 田泽, 郭亮, 等.符合OpenGL标准的国产化显卡研究与实现[J].计算机技术与发展, 2014(5) :173-175. DOI: 173

WU J, HUA G X, LIU H J. SoC Research AND Application Of Verification Methodology[J]. Space Control Technology And Application. 2012, 38(5) : 27-33. DOI: 27

韩俊刚.一种图形加速器和着色器的体系结构.计算机辅助设计与图形学学报[J]. 2010, 2(3): 363-372. DOI: 363

武凤丹, 阙恒, 王渊峰.一种新的低功耗高性能绘图芯片GPU设计方案[J].集成电路应用. 2017, 34(6): 33-36. DOI: 33

袁扬智, 韦明, 曾献军.2D图像硬件加速引擎的设计优化[J].微电子学与计算机, 2009, 26(4): 241-248. DOI: 241

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