A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture

DU Gao-ming; HU Guo-qing; LIN Qing; ZHANG Duo-li; SONG Yu-kun; Ouyang Yi-ming

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A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture

更新时间：2026-09-04

- A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture
- Vol. 36, Issue 12, Pages: 11-15(2019)
- 作者机构：
  
  合肥工业大学电子科学与应用物理学院,合肥,230009
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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杜高明, 胡国庆, 林青, 张多利, 宋宇鲲, 欧阳一鸣. 一种基于预判机制的极化码译码算法及VLSI架构[J]. 微电子学与计算机, 2019, 36(12): 11-15, 20.

DU Gao-ming, HU Guo-qing, LIN Qing, et al. A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture[J]. 2019, 36(12): 11-15.
杜高明, 胡国庆, 林青, 张多利, 宋宇鲲, 欧阳一鸣. 一种基于预判机制的极化码译码算法及VLSI架构[J]. 微电子学与计算机, 2019, 36(12): 11-15, 20. DOI：

DU Gao-ming, HU Guo-qing, LIN Qing, et al. A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture[J]. 2019, 36(12): 11-15. DOI：

摘要

本文提出一种基于对数似然比的预判机制

根据每层对数似然比符号直接判决分裂成"1"或者"0"和固定比特层直接分裂成已知比特

旨在减少路径分裂以及通过直接继承上一层路径度量值的方式

移除冗余的路径度量值计算.基于该机制

我们设计码长=1 024

码率=0.5

列表宽度=2的VLSI硬件架构.实验结果表明

其工作频率在384 MHz下

能达到约160 Mbps的吞吐率

延迟降低约51%.

Abstract

This paper proposes a pre-judgment mechanism based on log-likelihood ratio

reducing redundant split for SCL (RRS-SCL). According to the log-likelihood ratio symbol decision of each layer

it is split into "1" or "0" and the fixed bit layer are directly split into known bits

which aims to reduce path splitting and remove redundant path metric calculations by directly inheriting the path metrics from the previous layer. Based on the scheme

we design RRS-SCL VLSI architecture with code length N=1024

the code rate R=0.5

and the list width L=2. The experimental results show that the throughput can be achieved at 160Mbps under 384MHz and delay is reduced by approximately 51%.

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references

SASOGLU E, TELATAR I E, ARIKAN E. Polarization for arbitrary discrete memoryless channels[C]//2009 IEEE Information Theory Workshop. Taormina, Italy: IEEE, 2009: 144-148.

ARIKAN E. Channel polarization: A method for constructing capacity-achieving codes[C]//2008 IEEE International Symposium on Information Theory. Toronto, ON, Canada: IEEE, 2008: 1173-1177.

LIU X, SHA J, ZHANG C, et al. A stage-reduced low-latency successive cancellation decoder for polar codes[C]//2015 IEEE International Conference on Digital Signal Processing. Singapore, Singapore: IEEE, 2015: 258-262.

MORI R, TANAKA T. Performance and construction of polar codes on symmetric binary-input memoryless channels[C]//2009 IEEE International Conference on Symposium on Information Theory. Seoul, South Korea: IEEE, 2009: 1496-1500.

SHI S, HAN B, GAO J L, et al. Enhanced Successive Cancellation List Decoding of Polar Codes[J]. IEEE Communications Letters, 2017, 21(6):1233-1236. DOI: 1233

SARKIS G, GIARD P, VARDY A, et al. Fast List Decoders for Polar Codes[J]. IEEE Journal on Selected Areas in Communications, 2016, 34(2):318-328. DOI: 318

ARIKAN E. Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels[J]. IEEE Transactions on Information Theory, 2009, 55(7):3051-3073. DOI: 3051

BALATSOUKAS S A, BASTANI P M, BURG A. LLR-Based Successive Cancellation List Decoding of Polar Codes[J]. IEEE Transactions on Signal Processing, 2015, 63(19):5165-5179. DOI: 5165

YUAN B, PARHI K K. Low-Latency Successive-Cancellation List Decoders for Polar Codes with Multi-bit Decision[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(10):2268-2280. DOI: 2268

LIN J, XIONG C, YAN Z. A High Throughput List Decoder Architecture for Polar Codes[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(6):2378-2391. DOI: 2378

TAL I, VARDY A. List decoding of polar codes[C]//2011 IEEE International Symposium on Information Theory Proceedings. St. Petersburg, Russia: IEEE, 2011: 1-5.

LI B, SHEN H, TSE D. An Adaptive Successive Cancellation List Decoder for Polar Codes with Cyclic Redundancy Check[J]. IEEE Communications Letters, 2012, 16(12):2044-2047. DOI: 2044

KONG B Y, YOO H, PARK I C. Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 63(7):673-677. DOI: 673

PIAO Z, KIM Y J, CHUNG J G. Efficient successive cancellation decoder for polar codes based on frozen bits[C]// 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). Jeju, South Korea: IEEE, 2016: 585-587.

BIOGLIO V, GABRY F, GODARD L, et al. Two-Step Metric Sorting for Parallel Successive Cancellation List Decoding of Polar Codes[J]. IEEE Communications Letters, 2017, 21(3):456-459. DOI: 456

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