A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols

LI Mao; JIA Chen; LUAN Wen-huan; LIN Xin; WANG Zi-qiang; ZHANG Chun; Wang Zhi-hua

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A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols

更新时间：2026-09-04

- A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols
- Vol. 36, Issue 9, Pages: 16-20(2019)
- 作者机构：
  
  1. 清华大学微电子学研究所,北京,100084
  2. 深圳清华大学研究院机构,广东,深圳,518057
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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李貌, 贾晨, 栾文焕, 林鑫, 王自强, 张春, 王志华. 多协议可变位宽40 bits高速串口发射机[J]. 微电子学与计算机, 2019, 36(9): 16-20.

LI Mao, JIA Chen, LUAN Wen-huan, et al. A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols[J]. 2019, 36(9): 16-20.
李貌, 贾晨, 栾文焕, 林鑫, 王自强, 张春, 王志华. 多协议可变位宽40 bits高速串口发射机[J]. 微电子学与计算机, 2019, 36(9): 16-20. DOI：

LI Mao, JIA Chen, LUAN Wen-huan, et al. A high speed transmitter with 40 bits data and variable data-width and supported multi-protocols[J]. 2019, 36(9): 16-20. DOI：

摘要

本文提出一种多协议

可变位宽发射机系统

最高数据位宽40 bits

最高数据速率10.312 5 Gbps.整个系统由归一化数据位宽(Normalization of Data Width

NMDW)变换电路

40:1合路器(MUX)

时钟分布电路及3抽头前馈均衡器(Feed-Forward-Equalizer

FFE)组成

文章中提出了改进的40:1 MUX电路结构.本文采用SMIC 40 nm CMOS工艺

电源电压1.1 V.发射机(Transmitter

TX)整体功耗34mW@10.3125 Gbps

信道前差分输出眼图最大幅度大于800 mV.同时

本发射机支持4种不同协议

7种不同数据速率

9种工作状态

工作温度范围-45℃~125℃.

Abstract

This paper propose a system of transmitter(TX) supported multi-protocols and variable data-width

with max input data width of 40bits and data rate of 10.312 5 Gbps. The transmitter consists of Normalization of Data Width(NMDW)

40:1MUXs

distributed clock circuit and 3-taps Feed-Forward-Equalizer(FFE). This paper is proposed an improved 40:1MUXs circuit. and supported in SMIC 40nm CMOS technology

supported by 1.1 V. The power consumption of TX is 34.5mW@10.312 5 Gbps. The differential eye diagram is larger than 800 mV before channel. Meanwhile

TX is supported 4 different protocols

7 different data-rate

9 work conditions

the work temperature ranged from -45℃to 125℃.

关键词

Keywords

references

PHILPOTT R A, HUMBLE J S, KERTIS R A, et al. A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS[C]//CICC 2008. San Jose, CA, USA, 2008: 623-626.

ZHANG B, KARAPET KHANOYAN, TONG H T, et al. A 28Gb/s multistandard serial link transceiver for backplane applications in 28nm CMOS[C]//JSSC 2015. [S.l], 2015: 3089-3100.

BIMAN CHATTOPADHYAY, SHARATH N BHAT, GOPALKRISHNA NAYAK, et al.A 12.5Gbps transmitter for multi-standard serdes in 40 nm low leakage CMOS process[C]//VLSI 2018. Honolulu, HI, USA, 2018.

JRI LEE, KE-CHUNG WU. A 20-Gb/s Full-rate linear clock and data recovery circuit with automatic frequency acquisition[C]// JSSC 2009. [S.l], 2009: 3390-3602.

PENG P J, LI J F, CHEN L Y, et al. A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS[C]//ISSCC 2017. San Francisco, CA, USA, 2017: 110-112.

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