Design of 3D NAND flash memory on-chip control logic circuit

WANG Mei-lan; WANG Qi; CHEN Zhen-jia; LIU Zhi; ZHANG Ju-ping; HUO Zong-liang

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Design of 3D NAND flash memory on-chip control logic circuit

更新时间：2026-09-04

- Design of 3D NAND flash memory on-chip control logic circuit
- Vol. 36, Issue 6, Pages: 31-34(2019)
- 作者机构：
  
  1. 中国科学院大学机构,北京,101408
  2. 中国科学院机构微电子研究所,北京,100029
  3. 长江存储科技有限公司,湖北,武汉,430205
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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王美兰, 王颀, 陈振家, 刘志, 张桔萍, 霍宗亮. 3D NAND Flash的片上控制逻辑电路设计[J]. 微电子学与计算机, 2019, 36(6): 31-34, 39.

WANG Mei-lan, WANG Qi, CHEN Zhen-jia, et al. Design of 3D NAND flash memory on-chip control logic circuit[J]. 2019, 36(6): 31-34.
王美兰, 王颀, 陈振家, 刘志, 张桔萍, 霍宗亮. 3D NAND Flash的片上控制逻辑电路设计[J]. 微电子学与计算机, 2019, 36(6): 31-34, 39. DOI：

WANG Mei-lan, WANG Qi, CHEN Zhen-jia, et al. Design of 3D NAND flash memory on-chip control logic circuit[J]. 2019, 36(6): 31-34. DOI：

摘要

本文设计并实现了基于MCU的控制逻辑电路

并在仿真环境下进行了功能验证

用Design Compiler完成逻辑综合.结果表明

MCU工作正常

所占面积为0.35 mm

在33 MHz的工作频率下动态功耗为7.52 mW

符合设计目标.与传统的控制逻辑电路相比

基于MCU的控制逻辑电路具有更高的可修改灵活性

极大降低了升级产品的流片成本

缩短控制逻辑电路设计更新周期约50%.

Abstract

This paper presents an implementation based on MCU as the control logic circuit for 3D NAND Flash. The proposed circuit has passed functional verification in simulation environment and been synthesized by Design Compiler. Its area is 0.35mm

and the dynamic power consumption is 7.52mW at 33MHz operating frequency. Compared with the traditional design

control logic circuit based on MCU is easier to be modified

which can greatly reduce the tape out cost of the upgraded product and shorten upgrade cycle by approximately 50%.

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references

WORKGROUPO. Open NANDFlash interface specification[Z]. Revision, 2014, 2: 1-174.

PARK K T, BYEON D S, KIM D H. A world's first product of three-dimensional vertical NAND Flash memory and beyond[C]// Non-Volatile Memory Technology Symposium, South Korea, 2015: 1-5.

PARK K T, KIM D, HWANG S, et al. A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure[C]// International Solid-State Circuits Conference, USA, 2008: 510-632.

MAROTTA G G, MACEROLA A, D ALESSANDRO A, et al. A 3bit/Cell 32Gb NAND Flash Memory at 34nm with 6MB/s Program Throughput and with Dynamic 2b/Cell Blocks Configuration Mode for a Program Throughput Increase up to 13MB/s[C]//International Solid-State Circuits Conference, USA, 2010: 444-445.

IM J-W, JEONG W, KIM D-H, et al. A 128Gb 3b/cell V-NAND Flash memory with 1Gb/s I/O rate[C]// International Solid-State Circuits Conference, USA, 2015: 1-3.

Berlin CAMPARDO G, MICHELONI R, NOVOSEL D. VLSI-Design of Non-Volatile Memories[M]. Berlin:Springer Press, 2005.448-449. DOI: 448

SHIN S H, SHIM D K, JEONG J Y, et al. A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND Flash memory[C]// Symposium on VLSI Circuits, USA, 2012: 132-133.

PARK K T, NAM S, KIM D, et al. Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming[J]. IEEE Journal of Solid-State Circuits, 2014, 50(1):204-213. DOI: 204

SILVAGNI A, FUSILLO G, RAVASIO R, et al. An overview of logic architectures inside Flash memory devices[J]. Proceedings of the IEEE, 2003, 91(4):569-580. DOI: 569

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