Design of multiplier based on new compressor

ZHONG Ya; YE Yao-yao

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Design of multiplier based on new compressor

更新时间：2026-09-04

- Design of multiplier based on new compressor
- Vol. 36, Issue 3, Pages: 28-31(2019)
- 作者机构：
  
  上海交通大学微纳电子学系,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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仲亚, 叶瑶瑶. 基于新型压缩器的乘法器设计[J]. 微电子学与计算机, 2019, 36(3): 28-31, 37.

ZHONG Ya, YE Yao-yao. Design of multiplier based on new compressor[J]. 2019, 36(3): 28-31.
仲亚, 叶瑶瑶. 基于新型压缩器的乘法器设计[J]. 微电子学与计算机, 2019, 36(3): 28-31, 37. DOI：

ZHONG Ya, YE Yao-yao. Design of multiplier based on new compressor[J]. 2019, 36(3): 28-31. DOI：

摘要

为了优化乘法器的延时以及功耗

提高乘法器的性能

针对乘法器的部分积压缩部分设计了新型的压缩器以及新型的压缩算法

在此基础上设计实现了新型的18位乘法器.新型压缩器针对常规压缩器横向进位占用延时过大的的特点

通过优化横向进位传递方式来缩短延时; 新型的压缩算法采用二叉树结构进行并行处理

与常规的树结构相比

其布线简单

结构规则.基于simc 40 nm工艺

对18位乘法器进行综合.经过仿真验证

该乘法器关键路径延时2.43 fs

优于同类乘法器.

Abstract

In order to optimize the delay and power consumption of the multiplier

a new compressor and a new compression algorithm are designed for the partial product compression part of the multiplier. Based on this

a new design of 18 bit multiplier is proposed and implemented. The new compressor reduces the delay by optimizing the lateral carry path for the characteristic that the conventional compressor has a large time lag for lateral carry. The new compression algorithm uses a binary tree structure for parallel processing

and compared with the conventional tree structure

its wiring is simple and its structure is regular.

关键词

Keywords

references

NAJAFI A, TIMARCHI S. High-speed energy-efficient 5: 2 compressor[C]//2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO). Opatija, 2014: 80-84.

PISHVAIE A, JABERIPUR G, JAHANIAN A. Redesigned CMOS (4; 2) compressor for fast binary multipliers[J]. Canadian Journal of Electrical and Computer Engineering, 2013, 36(3): 111-115. DOI: 111

VEERAMACHANENI S, KRISHNA K M, AVINASH L, et al. Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors[C]//20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID′07). Bangalore, 2007: 324-329.

DORNELLES R, PAIM G, SILVEIRA B, et al. A power-efficient 4-2 adder compressor topology[C]//2017 15th IEEE International New Circuits and Systems Conference (NEWCAS). Strasbourg, 2017: 281-284.

ABHILASH R, DUBEY S, CHINNAAIAH M C. Asic design of low power VLSI architecture for different multiplier algorithms using compressors[C]//2016 11th International Conference on Industrial and Information Systems (ICIIS). Roorkee, 2016: 387-392.

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Related Author

ZHAI Zhao-yue

HAN Zhi-gang

Related Institution

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