In order to solve the problem of high-speed transmission of massive data

this paper uses AXIe (advanced TCA extensions for instrumentation) bus as the transmission architecture

and focuses on the design of data cache and transmission interface

and designs time-interleaved data acquisition module to complete AXIe data acquisition and transmission interface verification. The time-interleaved data sampling function is realized by two ADCs

and DDR3 is used as a deep storage unit of data

and high-speed data transmission is realized by using PCI Express. The design was done on the FPGA and functional verification using the ILA embedded logic analyzer. The results show that the design can achieve the interleaving sampling function well and complete the data transmission based on AXIe bus.