Design and implementation of a fully interconnected reconfigurable array

WU Hao-yue; DENG Jun-yong; Shan Rui; HE Fei-long; LIU Xin-chuang

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Design and implementation of a fully interconnected reconfigurable array

更新时间：2026-09-04

- Design and implementation of a fully interconnected reconfigurable array
- Vol. 36, Issue 10, Pages: 59-64(2019)
- 作者机构：
  
  1. 西安邮电大学电子工程学院,陕西,西安,710121
  2. 西安邮电大学计算机学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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吴皓月, 邓军勇, 山蕊, 贺飞龙, 刘新闯. 向下全互连可重构阵列设计与实现[J]. 微电子学与计算机, 2019, 36(10): 59-64.

WU Hao-yue, DENG Jun-yong, Shan Rui, et al. Design and implementation of a fully interconnected reconfigurable array[J]. 2019, 36(10): 59-64.
吴皓月, 邓军勇, 山蕊, 贺飞龙, 刘新闯. 向下全互连可重构阵列设计与实现[J]. 微电子学与计算机, 2019, 36(10): 59-64. DOI：

WU Hao-yue, DENG Jun-yong, Shan Rui, et al. Design and implementation of a fully interconnected reconfigurable array[J]. 2019, 36(10): 59-64. DOI：

摘要

可重构电路的灵活性是电路中的绝对优势

但其电路互连资源有限、PE (Processing Element)资源利用率低.向下全互连可重构阵列结构实现了阵列中每个PE与下一行PE的全连接

提高了PE资源利用率、整体数据处理速度.本设计使用modelsim、quartus分别进行了功能仿真、综合下载

结果表明所设计的可重构数据流处理单元能够进行多种配置的可重构.通过验证FFT算法在向下全互连的可重构阵列上的映射

结果显示可重构数据流处理单元成功实现了预期功能

并且满足其时序等要求.综合结果显示

4*4的可重构阵列

包括其外围电路

共占用19429(58%)门逻辑资源

支持76.07 MHZ的工作频率; 单个的可重构数据流处理器占用2565(8%)门逻辑资源

支持最高108.96 MHZ的工作频率.

Abstract

The flexibility of the reconfigurable circuit is an absolute advantage in the circuit

but its circuit interconnection resources are limited

and the utilization of PE (Processing Element) resources is low. The downward fully interconnected reconfigurable array structure realizes full connection between each PE and the next row of PEs in the array

improving PE resource utilization and overall data processing speed. This design uses modelsim and quartus to perform functional simulation and comprehensive downloading. The results show that the reconfigurable data stream processing unit can be reconfigurable in various configurations. By verifying the mapping of the FFT algorithm on the fully interconnected reconfigurable array

the results show that the reconfigurable data stream processing unit successfully implements the expected functionality and meets its timing requirements. The combined results show that 4*4 reconfigurable arrays

including its peripheral circuits

occupy a total of 19

429 (58%) gate logic resources

supporting a working frequency of 76.07 MHz; a single reconfigurable data stream processor occupies 2565 (8%) The gate logic resource supports a working frequency of up to 108.96 MHz.

关键词

Keywords

references

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