A fast and efficient compiler framework for CGRAs

YIN Wen-zhi; ZHAO Zhong-yuan; MAO Zhi-gang; WANG Qin; SHENG Wei-guang

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A fast and efficient compiler framework for CGRAs

更新时间：2026-09-04

- A fast and efficient compiler framework for CGRAs
- Vol. 36, Issue 8, Pages: 45-48(2019)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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尹文志, 赵仲元, 毛志刚, 王琴, 绳伟光. 一种快速高效的粗粒度可重构架构编译框架[J]. 微电子学与计算机, 2019, 36(8): 45-48, 53.

YIN Wen-zhi, ZHAO Zhong-yuan, MAO Zhi-gang, et al. A fast and efficient compiler framework for CGRAs[J]. 2019, 36(8): 45-48.
尹文志, 赵仲元, 毛志刚, 王琴, 绳伟光. 一种快速高效的粗粒度可重构架构编译框架[J]. 微电子学与计算机, 2019, 36(8): 45-48, 53. DOI：

YIN Wen-zhi, ZHAO Zhong-yuan, MAO Zhi-gang, et al. A fast and efficient compiler framework for CGRAs[J]. 2019, 36(8): 45-48. DOI：

摘要

利用硬件和软件协同的设计技术来进一步提高粗粒度可重构加速器在处理循环时的编译时间与面积效率(单位面积的性能).在硬件方面将处理单元内部的寄存器堆结构优化

用旁路互联的方式替代.软件方面基于这种结构提出了一种新颖

高效的循环映射算法.该算法相对于同期的研究算法

极大的缩小了搜索最优解决方案的空间.利用前向贪婪和反向回溯迭代运行

可以获得快速而又稳定的编译时间

同时保证了接近最优解的性能.在上述硬件与软件协同的解决方案下

架构的面积与计算效率得到了提升.实验数据显示

将本文的编译框架与最新技术比较

编译速度可提升1955倍

面积效率提升到1.36倍.

Abstract

This paper provides a hardware and software co-design technique to optimize the compilation time and area efficiency of loop acceleration on Coarse-Grained Reconfigurable Architectures (CGRAs). From the hardware prospective

the architecture of each processing element (PE) is optimized by replacing register file within PE with bypass logic. On the software side

we develop a novel and efficient loop mapping algorithm

which greatly shrinks the search space for the optimal solution. The iteration of forward greedy placement and backward recovery obtains a fast and stable compile speed and guarantees performance close to the optimal solution.This hardware and software co-design method improves the area and computation efficiency. Experiment result shows that our framework improves1955xin compile speed and obtainsa 1.25x area efficiency.

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references

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