Standardized, configurable universal design for onboard solid state memory controllers

ZHANG Wei-dong; DONG Zhen-xing; ZHU Yan; AN Jun-she

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Standardized, configurable universal design for onboard solid state memory controllers

更新时间：2026-09-04

- Standardized, configurable universal design for onboard solid state memory controllers
- Vol. 36, Issue 9, Pages: 61-66(2019)
- 作者机构：
  
  1. 中国科学院机构复杂航天系统电子信息技术国防科技创新重点实验室,北京,100190
  2. 中国科学院国家空间科学中心,北京,100190
  3. 中国科学院大学机构
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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张伟东, 董振兴, 朱岩, 安军社. 星载固态存储控制器标准化、可配置通用设计[J]. 微电子学与计算机, 2019, 36(9): 61-66.

ZHANG Wei-dong, DONG Zhen-xing, ZHU Yan, et al. Standardized, configurable universal design for onboard solid state memory controllers[J]. 2019, 36(9): 61-66.
张伟东, 董振兴, 朱岩, 安军社. 星载固态存储控制器标准化、可配置通用设计[J]. 微电子学与计算机, 2019, 36(9): 61-66. DOI：

ZHANG Wei-dong, DONG Zhen-xing, ZHU Yan, et al. Standardized, configurable universal design for onboard solid state memory controllers[J]. 2019, 36(9): 61-66. DOI：

摘要

为解决目前星载固态存储系统通用性差的问题

采用标准片上总线(APB总线)架构以及引入参数配置层的方法

设计了一种通用星载固态存储控制器.该设计可支持不同FLASH芯片厂家、不同FLASH芯片容量

以及不同叠装构型的NAND型FLASH存储阵列

从而实现一套代码可适应多种工程任务需求

可有效降低开发成本、缩短开发流程、提高开发效率.方案支持FLASH读写、擦除、复位等功能

并具备坏块管理机制

可以有效地增强系统的稳定性和提高存储效率.实验结果表明

系统支持最大写入速率达到100 Mbps、容量可达256 Gbit

并能够适配不同FLASH芯片构型以及兼容主流的宇航级FLASH芯片.

Abstract

To solve the problem of poor universality of the on-board solid-state storage system

a general on-board solid-state storage controller is designed by using the standard on-chip bus (APB bus) architecture and the method of introducing the parameter configuration layer. The design can support different FLASH chip manufacturers

different FLASH chip capacities

and NAND FLASH memory arrays with different stacked configurations

so that a set of codes can be adapted to various engineering tasks

which can effectively reduce development costs

shorten the development process and improve development efficiency. The design supports FLASH read/write

erase

reset and other functions

and has a bad block management mechanism

which can effectively enhance the stability of the system and improve storage efficiency. The experimental results show that the design has a maximum write rate of 100 Mbps and a maximum capacity of 256 Gbit

which can adapt to different FLASH chip configurations and compatible with mainstream aerospace FLASH chips.

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Keywords

references

李姗, 宋琪, 朱岩, 等.一种高可靠星载大容量存储器的坏块表存储方案设计[J].微电子学与计算机, 2016, 33(4):73-76. DOI: 73

朱岩.基于闪存的星载高速大容量存储技术的研究[D].北京: 中国科学院研究生院(空间科学与应用研究中心), 2006.

冉计全, 郭林, 张三刚, 等.NAND Flash控制器硬件设计与仿真验证[J].西北工业大学学报, 2017, 35(2):304-309. DOI: 304

高闯, 吴利华, 芳罗, 等.一种用于FPGA的可配置存储器设计[J].固体电子学研究与进展, 2016, 36(1):66-70. DOI: 66

董振兴, 朱岩, 许志宏, 等.星载存储器吞吐率瓶颈与高速并行缓存机制[J].哈尔滨工业大学学报, 2017, 49(11):52-59. DOI: 52

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