HLS-based design and optimization methodology for convolutional neural network

PENG Xin-Lei; YU Le

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HLS-based design and optimization methodology for convolutional neural network

更新时间：2026-09-04

- HLS-based design and optimization methodology for convolutional neural network
- Vol. 36, Issue 8, Pages: 63-67(2019)
- 作者机构：
  
  1. 北京工商大学计算机与信息工程学院,北京,100048
  2. 食品安全大数据技术北京市重点实验室,北京,100048
- 作者简介：
- 基金信息：
- DOI：
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- Published：2019
- 稿件说明：
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彭鑫磊, 余乐. 基于高层次综合的卷积神经网络设计与优化方法研究[J]. 微电子学与计算机, 2019, 36(8): 63-67.

PENG Xin-Lei, YU Le. HLS-based design and optimization methodology for convolutional neural network[J]. 2019, 36(8): 63-67.
彭鑫磊, 余乐. 基于高层次综合的卷积神经网络设计与优化方法研究[J]. 微电子学与计算机, 2019, 36(8): 63-67. DOI：

PENG Xin-Lei, YU Le. HLS-based design and optimization methodology for convolutional neural network[J]. 2019, 36(8): 63-67. DOI：

摘要

本文基于FPGA高层次综合的设计方法学

在ZYNQ-7020上实现了一个卷积神经网络加速器.采用循环展开和并行流水的设计方法对卷积核运算进行优化

均衡了所占用逻辑资源及运算效率

从而实现加速器的最优性能.通过MINST数据集在100MHz的工作频率下对加速器进行性能测试

结果表明:对单张图片

该加速器相对于通用平台ARM A9可实现3.77倍加速

而对1000张图片的流式处理可实现高达6.14倍加速.

Abstract

Based on High Level Synthesis (HLS) design methodology of FPGA

this paper implements a convolutional neural network accelerator on ZYNQ-7020. The design method of cyclic unroll and pipelinling is used to optimize the convolution kernel operation

and the occupied logic resources and operation efficiency are balanced to achieve the optimal performance of the accelerator. The performance of the accelerator is tested by the MINST dataset at 100MHz working frequency. The results show that:the accelerator can achieve 3.77 times acceleration compared to the general platform ARM A9for a single picture

and the streaming processing of thousands of pictures can achieve up to 6.14 times acceleration.

关键词

Keywords

references

范秋香. FPGA高级开发技术的研究[D].北京: 北京理工大学, 2015.

ZHANG C, LI P, SUN G, et al. Optimi-zing fpgabased accelerator design for deep convolutional neural networks[C]// Acm/sigda International Symposium on Field-programmable Gate Arrays. ACM, 2015.

LI H, FAN X, JIAO L, et al.A high pe-rformance FPGA-based accelerator for large-scale convolutional neural netwo-rks[C]// 201626th International Conf-erence on Field Programmable Logic and Applications (FPL). IEEE, 2016.

陈岩, 李洋洋, 余乐, 等.基于卷积神经网络的手写体数字识别系统[J].微电子学与计算机, 2018, 35(2):71-74. DOI: 1

余子健, 马德, 严晓浪, 等.基于FPGA的卷积神经网络加速器[J].计算机工程, 2017, 43(1):109-114. DOI: 109

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