Design and implementation of high performance SIMT processor for machine learning

ZHANG Hong-wei; LI Tao; FENG Zhen-fu; JIA Rui

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Design and implementation of high performance SIMT processor for machine learning

更新时间：2026-09-04

- Design and implementation of high performance SIMT processor for machine learning
- Vol. 36, Issue 9, Pages: 79-83(2019)
- 作者机构：
  
  1. 西安邮电大学机构电子工程学院,陕西,西安,710121
  2. 西安邮电大学计算机学院,陕西,西安,710121
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2019
- 稿件说明：
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张宏伟, 李涛, 冯臻夫, 贾蕊. 机器学习高性能SIMT处理器的设计与实现[J]. 微电子学与计算机, 2019, 36(9): 79-83.

ZHANG Hong-wei, LI Tao, FENG Zhen-fu, et al. Design and implementation of high performance SIMT processor for machine learning[J]. 2019, 36(9): 79-83.
张宏伟, 李涛, 冯臻夫, 贾蕊. 机器学习高性能SIMT处理器的设计与实现[J]. 微电子学与计算机, 2019, 36(9): 79-83. DOI：

ZHANG Hong-wei, LI Tao, FENG Zhen-fu, et al. Design and implementation of high performance SIMT processor for machine learning[J]. 2019, 36(9): 79-83. DOI：

摘要

针对机器学习中出现的大数据量运算的问题

自主研发了一款高性能SIMT (Single Instruction Multiple Threads)架构处理器.采用特殊的四级流水线结构

通过可综合的Verilog HDL语言对电路进行描述

完成了数据的多线程并行运算.在XiLinx公司VirtexUltraSacle系列的xcvu440-flga2892-2-e FPGA上搭建仿真验证平台对整体电路进行功能验证

结果表明

本设计电路满足多线程并行处理机制.采用SYNOPSYS公司Design-Compile在SMIC 65nm CMOS工艺标准单元库进行综合验证

系统时钟最高工作频率为370 MHz

系统最大功耗为4.251 mw.

Abstract

Aiming at the problem of large data volume computing in machine learning

a high-performance SIMT (Single Instruction Multiple Threads) architecture processor was developed. Using a special four-stage pipeline structure

the circuit is described in a synthesizable Verilog HDL language

and multi-thread parallel computing of data is completed. The simulation verification platform was built on the xcvu440-flga2892-2-e FPGA of XiLinxVirtexUltraSacle series to verify the function of the whole circuit. The results show that the design circuit satisfies the multi-thread parallel processing mechanism. The SYNOPSYS Design-Compile is used for comprehensive verification in the SMIC 65 nm CMOS process standard cell library. The maximum operating frequency of the system clock is 370 MHz

and the maximum power consumption of the system is 4.251 mw.

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references

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李涛, 杨婷, 易学渊, 等.萤火虫2:一种多态并行机的硬件体系结构[J].计算机工程与科学, 2014, 36(2):191-200. DOI: 191

JINWOOK OH, GYEONGHOON KIM, JUNYOUNG PARK, et al. A simultaneous multi-threading heterogeneous object recognition processor with machine learning based dynamic resource management[J]. IEEE COOL Chips XV, 20 12: 1-3. DOI: 10. 1 109/COOLChips.20 12.62 16579.

徐元旭, 张超, 杨兵, 等.一种易实现的SIMT调度模型分析[J].微电子学与计算机, 2014, 31(1):25-28. DOI: 25

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