A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS

WANG Lin; SONG Li-mei; WANG Li-xin; LUO Jia-jun; HAN Zheng-sheng

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A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS

更新时间：2026-09-04

- A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS
- Vol. 36, Issue 9, Pages: 84-88(2019)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,浙江,杭州,310053
  2. 中国科学院大学机构
  3. 中国科学院硅器件技术重点实验室,北京,100029
  4. 北京中科新微特科技开发股份有限公司, 北学,100029
- 作者简介：
- 基金信息：
- DOI：
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- Published：2019
- 稿件说明：
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王琳, 宋李梅, 王立新, 罗家俊, 韩郑生. 一种提升抗单粒子能力的新型超结结构[J]. 微电子学与计算机, 2019, 36(9): 84-88.

WANG Lin, SONG Li-mei, WANG Li-xin, et al. A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS[J]. 2019, 36(9): 84-88.
王琳, 宋李梅, 王立新, 罗家俊, 韩郑生. 一种提升抗单粒子能力的新型超结结构[J]. 微电子学与计算机, 2019, 36(9): 84-88. DOI：

WANG Lin, SONG Li-mei, WANG Li-xin, et al. A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS[J]. 2019, 36(9): 84-88. DOI：

摘要

为了提升超结器件在空间辐照环境下的可靠性

针对额定电压为700 V的超结器件提出了一种新型结构.加固的结构在标准SJVDMOS平面栅的基础上刻蚀掉部分栅极

同时引入了一个肖特基接触来提升器件的抗单粒子能力.2D synopsyssentaurus TCAD对器件进行了仿真建模

并通过单粒子的瞬态仿真来评估器件的SEE性能

仿真结果表明加固之后的器件在单粒子效应下的整体安全工作区大幅增加

器件抗单粒子烧毁和抗单粒子栅穿的能力都明显提升

同时新型结构的电学性能也维持了良好的水平.

Abstract

In this paper

a new structure to improve the SEE performance for 700 V Super-Junction VDMOS is proposed. Part of the planar gate of the device is etched away

adding a Schottky contactto enhance the SEE performance.2D synopsyssentaurus TCAD is used to do simulation

and transient simulation is used to evaluate the SEE performance of the device. The simulation result shows that the overall safe working area of the device after reinforcement iseffectively increased

and the SEB and SEGR performance both improved significantly. At the same time

the electrical performance of the new structure also maintains a good level.

关键词

Keywords

references

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TITUS J L, WHEATLEY C F, BURTON D I, et al. Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression[J]. IEEE Transactions on Nuclear Science, 2002, 42(6):1928-1934. DOI: 1928

WANG Y, YU C H, DOU Z, et al. Single-Event burnout hardening of power UMOSFETs with integrated schottky diode[J]. IEEE Transactions on Electron Devices, 2014, 61(5):1464-1469. DOI: 1464

TITUS J L, WHEATLEY C F. Experimental studies of single-event gate rupture and burnout in vertical power MOSFETs[J]. IEEE Transactions on Nuclear Science, 2002, 43(2):533-545. DOI: 533

ALLENSPACH M, DACHS C, JOHNSON G H, et al. SEGR and SEB in n-channel power MOSFETs[J]. IEEE Transactions on Nuclear Science, 2002, 43(6):2927-2931. DOI: 2927

WANG Y, ZHANG Y, WANG L G, et al. Single-event burnout hardening of power UMOSFETs with optimized structure[J]. IEEE Transactions on Electron Devices, 2013, 60(6):2001-2007 DOI: 2001

ALLENSPACH M, BREWS J R, MOURET I, et al. Evaluation of SEGR threshold in power MOSFETs[J]. IEEE Transactions on Nuclear Science, 1994, 41(6):2160-2166. DOI: 2160

TITUS J L, WHEATLEY C F, GILLBERG J E, et al. A study of ion energy and its effects upon an SEGR-hardened stripe-cell MOS-FET technology [space-based systems][J]. Nuclear Science IEEE Transactions on, 2001, 48(6):1879-1884. DOI: 1879

HUANG S, AMARATUNGA G A J, UDREA F. Analysis of SEB and SEGR in super-junction MOSFETs[J]. Nuclear Science IEEE Transactions on, 2000, 47(6):2640-2647. DOI: 2640

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