Design and implementation of convolution neural network accelerator based on FPGA

ZHAI She-ping; QIU Cheng; YANG Yuan-yuan; LI Jing; JIANG Ting-ting

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Design and implementation of convolution neural network accelerator based on FPGA

更新时间：2026-09-04

- Design and implementation of convolution neural network accelerator based on FPGA
- Vol. 36, Issue 8, Pages: 83-86(2019)
- 作者机构：
  
  西安邮电大学机构计算机学院陕西省网络数据分析与智能处理重点实验室,陕西,西安,710121
- 作者简介：
- 基金信息：
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- Published：2019
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翟社平, 邱程, 杨媛媛, 李婧, 江婷婷. 基于FPGA的卷积神经网络加速器设计与实现[J]. 微电子学与计算机, 2019, 36(8): 83-86.

ZHAI She-ping, QIU Cheng, YANG Yuan-yuan, et al. Design and implementation of convolution neural network accelerator based on FPGA[J]. 2019, 36(8): 83-86.
翟社平, 邱程, 杨媛媛, 李婧, 江婷婷. 基于FPGA的卷积神经网络加速器设计与实现[J]. 微电子学与计算机, 2019, 36(8): 83-86. DOI：

ZHAI She-ping, QIU Cheng, YANG Yuan-yuan, et al. Design and implementation of convolution neural network accelerator based on FPGA[J]. 2019, 36(8): 83-86. DOI：

摘要

FPGA已广泛用于卷积神经网络的硬件加速器的实现.本文设计了一种基于FPGA的卷积神经网络加速器.主要利用卷积神经网络中固有的并行性来减少实时嵌入式应用所需带宽与资源使用

并将其在有限资源的ZC706开发板上实现

结果显示

在150 MHz的工作频率下

FPGA的峰值运算速度达到0.54 GOP/s

且功耗很小.

Abstract

FPGAs are widely used in the implementation of hardware accelerators for convolutional neural networks. This paper designs a FPGA-based CNN acceleration structure. It mainly utilizes the inherent parallelism in CNN to reduce the bandwidth and resource usage required by real-time embedded applications

and implements it on the ZC706 development board with limited resources. The results show that the FPGA operates at a frequency of 0.54 GOP/s and consumes very little power at 150 MHz.

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references

ZHANG C, LI P, SUN G, et al. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks[C]// ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Monterey, USA: ACM, 2015: 161-170.

ZHANG C, WU D, SUN J, et al. Energy-efficient CNN implementation on a deeply pipelined FPGA cluster[C]//Proceedings of the 2016 International Symposium on Low Power Electronics and Design. San Francisco, USA: ACM, 2016: 326-331.

WANG C, YU Q, GONG L, et al. DLAU: A Scalable Deep Learning Accelerator Unit on FPGA[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 36(3):513-517. DOI: 513

LI X, ZHANG G, HUANG H H, et al. Performance analysis of GPU-based convolutional neural networks[C]//International Conference on Parallel Processing. Philadelphia, USA: IEEE, 2016: 67-76.

QIU J, WANG J, YAO S, et al. Going deeper with embedded FPGA platform for convolutional neural network[C]//Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Monterey, USA: ACM, 2016: 26-35.

LOKHMOTOV A, FURSIN G. Optimizing convolutional neural networks on embedded platforms with OpenCL[C]//Proceedings of the 4th International Workshop on OpenCL. Vienna, Austria: ACM, 2016: 10-14.

李彦冬, 郝宗波, 雷航.卷积神经网络研究综述[J].计算机应用, 2016, 36(9):2508-2515. DOI: 2508

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