Circuit design of wide supply voltage input and multi-channel oscillator

ZHI Yu-xin; CAI Xiao-wu; ZHAO Hai-tao; XIA Rui-rui; LIU Hai-nan; LUO Jia-jun

Chinese

您当前的位置：

首页 >

文章列表页 >

Circuit design of wide supply voltage input and multi-channel oscillator

更新时间：2026-09-04

- Circuit design of wide supply voltage input and multi-channel oscillator
- Vol. 37, Issue 9, Pages: 1-5(2020)
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 中国科学院大学机构,北京,101408
  3. 中国科学院硅器件技术重点实验室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
移动端阅览
智玉欣, 蔡小五, 赵海涛, 夏瑞瑞, 刘海南, 罗家俊. 一种宽电源电压输入多通道振荡器的电路设计[J]. 微电子学与计算机, 2020, 37(9): 1-5.

ZHI Yu-xin, CAI Xiao-wu, ZHAO Hai-tao, et al. Circuit design of wide supply voltage input and multi-channel oscillator[J]. 2020, 37(9): 1-5.
智玉欣, 蔡小五, 赵海涛, 夏瑞瑞, 刘海南, 罗家俊. 一种宽电源电压输入多通道振荡器的电路设计[J]. 微电子学与计算机, 2020, 37(9): 1-5. DOI：

ZHI Yu-xin, CAI Xiao-wu, ZHAO Hai-tao, et al. Circuit design of wide supply voltage input and multi-channel oscillator[J]. 2020, 37(9): 1-5. DOI：

摘要

采用BCD工艺设计了一中宽电源电压输入、多通道张弛振荡器电路，文中提出的一种片上电源变换电路以及一种基于张弛振荡器的时钟产生电路，克服了宽电源范围供电情况下对低压振荡器的要求

在降低电压变换电路复杂性的同时降低了频率对电压的敏感性

可应用于单电源高压供电芯片.在电源电压VDDH为典型值24 V情况下，逻辑低电平VDDL温度系数为290 ppm/℃；电源电压从0跳变到24 V时，VDDL稳定5 V仅需0.16 s；27℃情况下，电源电压VDDH从7 V到40 V变换情况下，VDDL电平变化1.72%.27 ℃情况下，在7 V供电电压时，最大时钟偏移0.20%；在24 V供电电压时，最大时钟偏移0.21%.电路采用0.25 m工艺实现，在电源电压24 V，工作频率25 MHz时，电流消耗仅为150 A.

Abstract

This paper introduces a design of multi-channel relaxation oscillator circuit using BCD process wide power supply voltage input. An on-chip power conversion circuit and a clock generation circuit based on a relaxation oscillator are proposed to overcome the requirement of a low-voltage oscillator under a wide power supply range

and reduce the frequency-to-voltage sensitivity while reducing the complexity of the voltage conversion circuit. This circuit can be applied to a single power supply chip for a wide range of voltage changes. When the power supply voltage VDDH is a typical value of 24 V

the logic low level VDDL temperature coefficient is 290 ppm / ℃; when the power supply voltage changes from 0 to 24 V

VDDL is stable at 5 V and needs only 0.16 s. At 27 ℃

the VDDL level changes by 1.72% when the power supply voltage VDDH changes from 7 V to 40 V. At 27℃

the maximum clock offset is 0.20% at 7 V supply voltage and 0.21% at 24 V supply voltage.The circuit is implemented in CSMC 0.25 m process. When the power supply voltage is 24 V and the operating frequency is 25 MHz

current consumption is only 150 A.

关键词

Keywords

references

LEE J, PARKP, CHO S H, et al.A 4.7MHZ 53uW f-ullydiferential CMOS reference clock oscillator with 22dB worst-case PSRR for miniaturized SoCs[C]//International Solid-State Circuits Con-ference.SanFrancisio, CA, USA: IEEE press, 2015: 1-3.

Xi′an BEGZAD RAZAVI.Design of Analog CMOS Integ-rated Circuits[M].Xi′an:Xian Jiaotong University Press, 2013.

SYBNDARESAN K, ALLEN P E, AYAZI F. Process and temperature compensation in a 7MHz CMOS c-lock oscilator[J].IEEE Journal of Solid-State Ci-rcuits, 2006, 41(2):433-422. DOI: 433

CAO Y, YAN R J, HONG Z L.On-chip rela- xation oscillator with low temperature sensitivi ty [J].Microelectronics and Computer, 2018, 35(3):28-32. DOI: 28

O'CIBBELL T R, HARTMAN J M, ERRETT E B, et al.Two static 4K clocked and noncl ocked RAM designs[J].IEEE Journal of Solid-State Circuits, 1977, 12(5):479-501. DOI: 479

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Aerial vehicle detection algorithm based on multi-scale fusion and small-object enhancement

High gain stability high temperature operational amplifier based on reverse body bias

Design of ultra-low power real-time clock circuits

Steganography model guided by attention mechanism and improved dense convolution

A review of large model development: technological evolution from BERT to Deepseek

Related Author

No data

Related Institution

No data

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰