Implementation of channel estimation algorithms based on dynamic reconfigurable processor

ZHAO Can-kun; WANG Zi-qiang

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Implementation of channel estimation algorithms based on dynamic reconfigurable processor

更新时间：2026-09-04

- Implementation of channel estimation algorithms based on dynamic reconfigurable processor
- Vol. 37, Issue 7, Pages: 1-5(2020)
- 作者机构：
  
  清华大学微电子学研究所,北京,100084
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
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赵灿坤, 王自强. 基于动态可重构处理器的信道估计算法实现[J]. 微电子学与计算机, 2020, 37(7): 1-5, 11.

ZHAO Can-kun, WANG Zi-qiang. Implementation of channel estimation algorithms based on dynamic reconfigurable processor[J]. 2020, 37(7): 1-5.
赵灿坤, 王自强. 基于动态可重构处理器的信道估计算法实现[J]. 微电子学与计算机, 2020, 37(7): 1-5, 11. DOI：

ZHAO Can-kun, WANG Zi-qiang. Implementation of channel estimation algorithms based on dynamic reconfigurable processor[J]. 2020, 37(7): 1-5. DOI：

摘要

随着无线通信标准的快速发展与各个协议中操作模式数量的激增，为特定模式设计专用芯片的成本和时间难以承受.同时，使用通用微处理器来进行信号处理的速度过慢，难以满足需要.本文尝试在动态可重构处理器架构上实现一种MIMO-OFDM系统中典型的信道估计算法，可以兼顾硬件实现的灵活性与处理速度的高效性.在28 nm工艺下以1 GHz的时钟频率仿真，其处理速度可达通用微处理器的8.8到14.6倍.

Abstract

With the rapid development of wireless communication standards and the proliferation of operating modes in various protocols

the cost and time to design an ASIC for a particular mode is unbearable. At the same time

the use of a general-purpose microprocessor for signal processing is too slow to meet the needs. Therefore

this paper attempts to implement typical channel estimation algorithms in a MIMO-OFDM system on a dynamic reconfigurable processor architecture

which can balance the flexibility of hardware implementation and the efficiency of processing speed. It is simulated at a clock frequency of 1 GHz in 28 nm process

and its processing speed can reach 8.8 to 14.6 times of that of a general-purpose microprocessor.

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references

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CHIU P L, HUANG L Z, CHAI L W, et al. A 684Mbps 57mW joint QR decomposition and MIMO processor for 4×4 MIMO-OFDM systems[C]//IEEE Asian Solid-State Circuits Conference 2011. Jeju, Korea, 2011: 309-312.

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