Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR

LUAN Wen-huan; WANG Deng-jie; JIA Chen; WANG Zi-qiang

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Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR

更新时间：2026-09-04

- Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR
- Vol. 37, Issue 3, Pages: 1-4(2020)
- 作者机构：
  
  清华大学微电子学研究所,北京,100084
- 作者简介：
- 基金信息：
- DOI：
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- Published：2020
- 稿件说明：
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栾文焕, 王登杰, 贾晨, 王自强. 应用于10Gbase-KR的二阶时钟数据恢复电路的建模分析与电路设计[J]. 微电子学与计算机, 2020, 37(3): 1-4.

LUAN Wen-huan, WANG Deng-jie, JIA Chen, et al. Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR[J]. 2020, 37(3): 1-4.
栾文焕, 王登杰, 贾晨, 王自强. 应用于10Gbase-KR的二阶时钟数据恢复电路的建模分析与电路设计[J]. 微电子学与计算机, 2020, 37(3): 1-4. DOI：

LUAN Wen-huan, WANG Deng-jie, JIA Chen, et al. Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR[J]. 2020, 37(3): 1-4. DOI：

摘要

本文针对10 Gbase-KR的应用场合，设计了一款基于相位插值器的二阶CDR，通过对其进行线性建模分析，折中抖动容忍、锁定时间以及抖动峰值的关系，选取合适的增益系数，并采用SMIC 40 nm CMOS工艺完成了电路设计.其中二阶滤波器的比例和积分系数可调，可以追踪1 000 ppm的偏差，恢复时钟的抖动最差情况为24 ps.

Abstract

In this paper

a second-order CDR based on phase interpolator is designed for 10Gbase-KR. Through linear modeling and analysis

it makes a compromise between jitter tolerance

lock-in time and jitter peak value

and the appropriate gain coefficient is selected. The circuit is designed by SMIC 40 nm CMOS process

in which the ratio and integral coefficient of the second-order filter can be adjusted to track the deviation of 1 000 ppm

and the worst case of recovery clock jitter is 24 ps.

关键词

Keywords

references

花正贝.符合PCIe2.0规范的时钟数据恢复电路设计[D].合肥: 中国科学技术大学, 2016.

SONNTAG J L, STONICK J. A digital clock and data recovery architecture for multi-gigabit/s binary links[J]. IEEE Journal of Solid-State Circuits, 2006, 41(8): 1867-1875. DOI: 1867

王运锋. FT-SerDes CDR关键电路设计[D].长沙: 国防科学技术大学, 2015.

JRI LEE, KUNDERT K S, RAZAVI B. Analysis and modeling of bang-bang clock and data recovery circuits[J]. IEEE Journal of Solid-State Circuits, 2004, 39(9): 1571-1580. DOI: 1571

SUN Y, WANG H. Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers[C]//2009 IEEE Custom Integrated Circuits Conference. Rome, 2009: 343-346.

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