Design and research of task management mechanism based on RISC-V heterogeneous system

SU Peng; JING Nai-feng

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Design and research of task management mechanism based on RISC-V heterogeneous system

更新时间：2026-09-04

- Design and research of task management mechanism based on RISC-V heterogeneous system
- Vol. 37, Issue 9, Pages: 6-10(2020)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
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- Published：2020
- 稿件说明：
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苏鹏, 景乃锋. 基于RISC-V的异构系统任务管理机制设计与研究[J]. 微电子学与计算机, 2020, 37(9): 6-10.

SU Peng, JING Nai-feng. Design and research of task management mechanism based on RISC-V heterogeneous system[J]. 2020, 37(9): 6-10.
苏鹏, 景乃锋. 基于RISC-V的异构系统任务管理机制设计与研究[J]. 微电子学与计算机, 2020, 37(9): 6-10. DOI：

SU Peng, JING Nai-feng. Design and research of task management mechanism based on RISC-V heterogeneous system[J]. 2020, 37(9): 6-10. DOI：

摘要

随着当前面向特定领域加速器设计的快速发展，基于加速器的异构系统是计算架构设计发展的新趋势.但复杂的异构系统对编程方式以及处理器和加速器之间的高效交互提出了挑战.如何描述主处理器和加速器的计算任务，降低两者之间的数据传输代价，并让处理器高效地完成对加速器的任务管理调度是保证异构系统性能的关键技术.本文基于一种以数据流为驱动的可重构阵列，基于工作特点，通过对其驱动方式、数据流向、输入输出等进行抽象，提出了一种与主控之间任务管理机制和互连方式，包括硬件的主机接口，软件的任务管理系统等，并基于RISC-V指令集的Rocket Core上实现并验证.

Abstract

With the rapid development of design for specific fields accelerator

heterogeneous system based on accelerator is a new trend of computing architecture design. However

the complex heterogeneous system challenges the programming mode and the efficient interaction between processor and accelerator. How to describe the computing tasks between the main processor and the accelerator

and how to reduce the cost of data transmission between them

and how to make the processor efficiently complete the task management and scheduling of the accelerator are the key technology to ensure the performance of heterogeneous systems. Based on a reconfigurable array driven by data flow

this paper proposes a task management mechanism and interconnection mode with the master controller by abstracting its driving mode

data flow direction

input and output

including the host interface of hardware

task management system of software

etc.

which is implemented and verified on Rocket Core based on risc-v instruction.

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references

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