Through thealgorithm′s analysis and the characteristic of real-time speech signal processing

a frame rotation structure have been designed. In addition

the paralleled and pipelined structures are designed for the correlation calculation

the filtering

and the read-write accessing of SRAM processes during the algorithm′s chip development. And

a storage address control logic is designed

therefore

our design′s clock cycle is only 1/68 of the DSP hardware platform operation of each frame′s speech coding. Finally

the PESQ test is completed with a set of pink-noise mixture speeches. The experimental results indicate that the PESQ are all scored above 4.0 when the SNR is not lower than 5 dB. These prove that real-time

highly compressed bit-ratio

high quality speech coding functions are successfully achieved in our design of the chip.