Coarse-Grained Reconfigurable Architectures (CGRAs) are promising computing platform with better efficiency. However
too much cost is wasted on the path of context storage and transmitting. With statistics of real case
there is obvious similarity between context. We propose one kind of context reduction method based on similarity of context. By making context compress
transmit
and decompress
this method can reduce power and area of CGRA obviously
with little overhead on performance. We propose context dispensing and register model for homogeneous heterogeneous platform. With the optimize of compiler
we get 33% and 118% promotion on power efficiency to tradition architecture
36% and 181% on area efficiency.
关键词
Keywords
references
KARUNARATNE M, TAN C, KULKARNI A, et al. Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs[C]//2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). IEEE, 2018: 1-6.
KIM Y, MAHAPATRA R N. Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture[J]. IEEE Transactions on Very Large Scale Integration Systems, 2009, 18(1):15-28. DOI: 15
EGGER B, LEE H, KANG D, et al. A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures[C] // International Symposium on Code Generation % Optimization. IEEE Press, 2017.
LIU D, YIN S, LIU L, et al. Polyhedral model based mapping optimization of loop nests for CGRAs[C]//Proceedings of the 50th Annual Design Automation Conference. ACM, 2013: 19.
ASLAM, NAZISH, MILWARD, et al. Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures[J]. IEEE Transactions on Very Large Scale Integration Systems, 16(12):1596-1608. DOI: 1596
KIM Y, KIEMB M, PARK C, et al. Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization[C] // Proceedings of the conference on Design, Automation and Test in Europe-Volume 1. IEEE Computer Society, 2005: 12-17.
MEI B, VERNALDE S, VERKEST D, et al. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix[C] // International Conference on Field Programmable Logic and Applications. Springer, Berlin, Heidelberg, 2003: 61-70.
YIN W Z, ZHAO Z Y, MAO Z G, et al.A fast and efficient compiler frame work for CGRAs[J].Microelectronics % Computer, 2019, 36(8):45-48. DOI: 45
KIM Y, MAHAPATRA R N, PARK I, et al. Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(5):0-603. DOI: 0