Design of sparse convolutional neural network accelerator

LI Yong-bo; WANG Qin; JIANG Jian-fei

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Design of sparse convolutional neural network accelerator

更新时间：2026-09-04

- Design of sparse convolutional neural network accelerator
- Vol. 37, Issue 6, Pages: 30-34(2020)
- 作者机构：
  
  上海交通大学电子信息与电气工程学院,上海,200240
- 作者简介：
- 基金信息：
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- Published：2020
- 稿件说明：
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李永博, 王琴, 蒋剑飞. 稀疏卷积神经网络加速器设计[J]. 微电子学与计算机, 2020, 37(6): 30-34,39.

LI Yong-bo, WANG Qin, JIANG Jian-fei. Design of sparse convolutional neural network accelerator[J]. 2020, 37(6): 30-34.
李永博, 王琴, 蒋剑飞. 稀疏卷积神经网络加速器设计[J]. 微电子学与计算机, 2020, 37(6): 30-34,39. DOI：

LI Yong-bo, WANG Qin, JIANG Jian-fei. Design of sparse convolutional neural network accelerator[J]. 2020, 37(6): 30-34. DOI：

摘要

为降低卷积神经网络推断时的时延和能耗，使用动态网络剪枝技术得到稀疏网络并设计出高能效比的稀疏卷积神经网络加速器.针对运算负载不均衡问题，提出适合稀疏运算的数据流；针对卷积运算高时延问题，采用16×16运算阵列提高运算并行度，设计索引单元避免无效运算，设计脉动输入层加强数据复用，采用乒乓缓存减少数据等待.综合结果表明，在TSMC 28 nm工艺下，芯片工作频率可达500 MHz，功耗为249.7 mW，卷积运算峰值算力达到256 GOPS，能效比为1.03 TOPS/W.

Abstract

In order to reduce the latency and energy consumption of convolutional neural networks

dynamic network surgery is used to get sparse networks and a high energy efficiency sparse convolutional neural network accelerator is designed. Aiming at the problem of unbalanced computing load

a dataflow suitable for sparse computing is proposed. To reduce the latency of convolution operation

a 16×16 process engine array is used to improve computation parallelism

index units are designed to avoid invalid operation

the systolic input structure is designed to enhance data reuse

and ping-pong buffers are introduced to reduce data waiting. The synthesis results showthat the frequency can reach 500 MHz

the power consumption is 139mW

the peak performance is 221 GOPS

and the energy efficiency is 1.59T OPS/W with TSMC 28nm process.

关键词

Keywords

references

MOONS B, UYTTERHOEVEN R, DEHAENE W, et al. 14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI[C]// Solid-state Circuits Conference.San Francisco, USA: IEEE, 2017: 246-247.

ZHANG S, DU Z, ZHANG L, et al. Cambricon-X: An accelerator for sparse neural networks[C]// 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). Taipei, China: IEEE, 2016: 1-12.

HAN S, MAO H, DALLY W J. Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding[C]// International Conference on Learning Representations. San Juan, Puerto Rico, 2016: 1-14.

WANG Q, SHEN F, SHEN L, et al. Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network[J]. Journal of digital imaging, 2019, 32(6): 971-979. DOI: 971

ALESSANDRO A, HESHAM M, ENRICO C, et al. NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps[J]. IEEE Transactions on Neural Networks and Learning Systems, 2019, 30(3):644-656. DOI: 644

CHEN Y H, KRISHNA T, EMER J S, et al. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks[J]. IEEE Journal of Solid-State Circuits, 2017, 52(1): 127-138. DOI: 127

ZHOU A, YAO A, GUO Y, et al. Incremental network quantization: Towards lossless cnns with low-precision weights[J]. arXiv preprint arXiv: 1702.03044, 2017.

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