WANG Jun-jie, WAN Shu-qin, JI Hui-cai, et al. Design and implementation of 8B/10B parallel coding circuit for JESD204B protocol[J]. 2020, 37(6): 35-39.
WANG Jun-jie, WAN Shu-qin, JI Hui-cai, et al. Design and implementation of 8B/10B parallel coding circuit for JESD204B protocol[J]. 2020, 37(6): 35-39.DOI:
Design and implementation of 8B/10B parallel coding circuit for JESD204B protocol
This paper designs and implements a four-way parallel 8B/10B encoding circuit
which has been verified by NCVerilog simulation. It can work at 405 MHz under a 65-nm technology library
supporting 16.2 Gbps serial data transmission rate
occupying 1832m of logical resources. As the 8B/10B coding module in JESD204B protocol
it has been applied in the SerDes interface circuit of a high-speed ADC chip. The actual circuit test shows that the encoder meets the 12.5 Gbps maximum transmission rate requirement of JESD204B protocol standard.
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references
WIDMER A X, FRANASZEK P A.A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code[J].IBM Journal of Research and Development, 1983, 27(5): 440-451. DOI: 440
YADAV S, PANDEY S, GUPTA A. Implementation of 8B/10B encoder-decoder for Gigabit Ethernet Frame[C]//2014 Eleventh International Conference on Wireless and Optical Communications Networks (WOCN).IEEE, 2014: 1-4.