With the progress of manufacturing technology and the increasing of system-on-chip circuit functions

most modern system-on-chip integrate a variety of embedded static random-access memory

and the influence of three-cell coupling faults begins to deepen. The traditional memory built-in self-test method is usually implemented directly on the basis of electronic design automation tools

which is mainly used for detecting single and double cell faults

and the three-cell coupling faults cannot be comprehensively covered

and the problems of excessive testing overhead and low test coverage are also faced in the application of the modern system-on-chip. In this paper

a memory built-in self-test optimization design method for three-cell coupling faults based on the size

type

quantity and layout of embedded SRAM is proposed

which realize the balance and optimization of the scale and test time of SoC chip

reduce the test cost and increase the test coverage.