Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm

ZHOU Guo-fei; YANG Hong; YANG Yan-feng

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Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm

更新时间：2026-09-04

- Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm
- Vol. 37, Issue 9, Pages: 62-67(2020)
- 作者机构：
  
  公安部第一研究所机构,北京,100044
- 作者简介：
- 基金信息：
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- Published：2020
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周郭飞, 杨宏, 杨延峰. 基于自适应环路滤波算法的全数字锁相环设计与分析[J]. 微电子学与计算机, 2020, 37(9): 62-67.

ZHOU Guo-fei, YANG Hong, YANG Yan-feng. Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm[J]. 2020, 37(9): 62-67.
周郭飞, 杨宏, 杨延峰. 基于自适应环路滤波算法的全数字锁相环设计与分析[J]. 微电子学与计算机, 2020, 37(9): 62-67. DOI：

ZHOU Guo-fei, YANG Hong, YANG Yan-feng. Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm[J]. 2020, 37(9): 62-67. DOI：

摘要

环路滤波器是全数字锁相环中重要的模块，对环路的许多性能都有着重要的影响.为了加快锁定时间的同时降低带内噪声，本文提出了一种适用Ⅱ型全数字锁相环的自适应环路滤波算法.该算法预先选择多组对应带宽由大到小的环路滤波参数.在跟踪过程中，根据环路的状态依次在特定的时刻切换参数，并对因切换导致频率控制字跳变进行补偿.本文首先证明了自适环路滤波器的可行性，然后给出了算法的实现流程，最后采用Verilog-A语言在HSPICE中对上述算法进行了仿真实验.实验结果表明采用本文提出的自适应环路滤波，ADPLL锁定时间仅仅略大于第一组参数对应的锁定时间，而其锁定后的相位噪声与最后一组参数的相同.

Abstract

The digital Loop filter is a key module in all digital phase locked loop (ADPLL) and has an important impact on the performance of the loop. In order to shorten the settling time and reduce the in-band phase noise

this paper proposes a type Ⅱ ADPLL adaptive loop filtering algorithm. To implement the algorithm

several sets of loop filter parameters with large to small bandwidth are pre-selected. In the tracking process

the algorithm will switch those parameters orderly at a special time according to the state of the loop

and the non-ideal jump of frequency control word caused by the switching is compensated at the same time. Finally

this paper built a Type Ⅱ ADPLL with three sets of loop filtering parameters in HSPICE using Verilog-A language

and simulated the algorithm. The simulation results show that the total lock time of the loop is only slightly larger than that of the first set of parameters

and the phase noise characteristic after locking is the same as the last set of parameters.

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references

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