Design of a voltage reference based on JFET differential input pair

LI Fei; CHEN Na

Chinese

您当前的位置：

首页 >

文章列表页 >

Design of a voltage reference based on JFET differential input pair

更新时间：2026-09-04

- Design of a voltage reference based on JFET differential input pair
- Vol. 37, Issue 4, Pages: 80-85(2020)
- 作者机构：
  
  1. 中国电子科技集团公司第五十八研究所,江苏,无锡,214035
  2. 重庆市计量质量检测研究院机构,重庆,401123
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
移动端阅览
李飞, 陈娜. 一种基于JFET差分输入对的电压基准源设计[J]. 微电子学与计算机, 2020, 37(4): 80-85.

LI Fei, CHEN Na. Design of a voltage reference based on JFET differential input pair[J]. 2020, 37(4): 80-85.
李飞, 陈娜. 一种基于JFET差分输入对的电压基准源设计[J]. 微电子学与计算机, 2020, 37(4): 80-85. DOI：

LI Fei, CHEN Na. Design of a voltage reference based on JFET differential input pair[J]. 2020, 37(4): 80-85. DOI：

摘要

采用4 μm 40 V BJT商用工艺设计了一种基于JFET差分输入对的2.5 V电压基准源.内部结构包括JFET差分输入对、恒流源、PTAT电流源、运放、电阻分压器、短路保护.仿真结果表明本设计能够满足5 V~30 V宽电压范围、车规级温度范围应用，并具有低噪声、低温漂、低温度非线性等卓越性能.

Abstract

Fabricated by 4 μm 40 V BJT commercial technology

a designed voltage reference based on JFET differential input pair outputs 2.5V steadily

which is comprised of JFET differential input pair

constant current source

PTAT current source

op-amp

resistor divider

short-circuited protection. Simulation results show that the design lends itself well to a wide range of voltage application (5 V~30 V) and vehicle-level temperature application. Besides

low noise

low temperature drift

low temperature nonlinearity could also be expected.

关键词

Keywords

references

BROKAW PAUL. More About the AD580 Monolithic IC Voltage Regulator[J]. Analog Dialogue, 1975, 9(1):6-7. DOI: 6

WONG WAISUM W, LIOU JUIN J. JFET Ciruit Simulation Using SPICE Implemented with an Improved Model [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13(1):105-109. DOI: 105

奚冬杰, 杜士才.一种低温度系数高电源抑制比带隙基准[J].电子与封装, 2017, 17(12) :30-33. DOI: 30

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design of High Resolution Comparator for 16 Bit SAR ADC

Design of ultra-low power real-time clock circuits

Microservices anomaly detection based on the correlation of monitoring metrics

Implementation and verification of a dual-chain power gating strategy for low power design

Monte carlo analysis of V-layout trench SiC neutron detector

Related Author

HOU Bin

MO Ting-ting

Related Institution

School of Microelectronics, Shanghai Jiao Tong University

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰