Research of parallel acceleration method and implementation of normalized product correlation with FPGA

LI Hong-jun; GUO Yang; JIA Run

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Research of parallel acceleration method and implementation of normalized product correlation with FPGA

更新时间：2026-09-04

- Research of parallel acceleration method and implementation of normalized product correlation with FPGA
- Vol. 37, Issue 2, Pages: 80-86(2020)
- 作者机构：
  
  1. 国防科技大学,安徽,合肥,230031
  2. 天津津航计算技术研究所,天津,300308
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2020
- 稿件说明：
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李红军, 郭阳, 贾润. 归一化积相关算法并行加速方法研究及FPGA实现[J]. 微电子学与计算机, 2020, 37(2): 80-86.

LI Hong-jun, GUO Yang, JIA Run. Research of parallel acceleration method and implementation of normalized product correlation with FPGA[J]. 2020, 37(2): 80-86.
李红军, 郭阳, 贾润. 归一化积相关算法并行加速方法研究及FPGA实现[J]. 微电子学与计算机, 2020, 37(2): 80-86. DOI：

LI Hong-jun, GUO Yang, JIA Run. Research of parallel acceleration method and implementation of normalized product correlation with FPGA[J]. 2020, 37(2): 80-86. DOI：

摘要

归一化积相关算法在地形匹配、目标识别等图像处理中有着广泛的应用，但由于其计算过程复杂，计算实时性较差，限制了它的应用范围，本文结合FPGA在并行计算方面的优势，提出了一种归一化积相关16路并行计算方法及硬件实现架构，具有精度高、速度快的特点，并在FPGA上进行了实现，与PC机MATLAB软件和DSP芯片TS201相比，运算速度提升了上千甚至上万倍，计算精度能够达到10，能够满足地形匹配及目标识别等图像处理的实时性和计算精度要求.

Abstract

Normalized product correlation method is widely used in image processing filed

such as terrain matching and target recognition

and has limited application for complex computational process and insufficient real-time performance.In this paper

a 16-channel normalized product correlation parallel computing method and hardware architecture are proposed based on the advantages of FPGA in parallel computing. It is implemented on the FPGA and has the characteristics of high precision and fast speed.Compared with the PC MATLAB software and DSP chip TS201

the computing speed is increased by thousands or even tens of thousands of times

and the computing accuracy can reach 10

which can meet the real-time and precision and precision requirements of image processing such as terrain matching and target recognition.

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references

JAVIER TOLEDO-MOREO F, JAVIER MARTíNEZ-ALVAREZ J, JAVIER GARRIGóS-GUERRRE F, et al. FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size[J]. Journal of Systems Architecture, 2012, 58(8): 277-285. DOI: 277

NNADANA N, DIVYA KIRAN, HARIHARAN RAMASANGU. FPGA Implementation of Efficient Convolution Architecture for CNN[J]. RUAS-SAS Tech Journal, 2017, 17(1): 25-28. DOI: 25

ALMUDENA LINDOSO, LUIS ENTRENA. High performance FPGA-based image correlation[J]. Journal of Real-Time Image Processing. 2007, 2(4): 223-233. DOI: 223

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朱永松, 国澄明.基于相关系数的相关匹配算法的研究[J].信号处理, 2003, 19 (6) : 531-534. DOI: 531

AMILA CABRAL, AJITH PASQUAL. FPGA Implementation of Normalized Cross-Correlation for Real-time Template Matching in Dynamic Search Windows[C]//17th ERU Research Symposium, 2011: 121-124.

ARRIGO BENEDETTI, ANDREA PRATI, NELLO SCARABOTTOLO. Image Convolution on FPGAs: the Implementation of a Multi- FPGA FIFO Structure[C]//Proceedings of the 24th Euromicro Conference, 1998: 123-130.

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